GB1451084A - Integrated semiconductor memories - Google Patents

Integrated semiconductor memories

Info

Publication number
GB1451084A
GB1451084A GB5677073A GB5677073A GB1451084A GB 1451084 A GB1451084 A GB 1451084A GB 5677073 A GB5677073 A GB 5677073A GB 5677073 A GB5677073 A GB 5677073A GB 1451084 A GB1451084 A GB 1451084A
Authority
GB
United Kingdom
Prior art keywords
regions
layer
constituted
collectors
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5677073A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1451084A publication Critical patent/GB1451084A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0828—Combination of direct and inverse vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors

Abstract

1451084 Semiconductor integrated memories HITACHI Ltd 7 Dec 1973 [8 Dec 1972] 56770/73 Heading H1K An integrated semiconductor memory stage (Fig. 1) a plurality of which may be contained in a single substrate comprises a P-type substrate 1b a N<SP>+</SP> type layer 10a buried therein, a P-layer 2b epitaxially grown thereon with low impurity concentration, and a N<SP>+</SP> layer formed in layer 2b by e.g. in-diffusion of N<SP>+</SP> impurity. Inverse transistors T 1 , T 2 have emitters constituted by exposed portions of N<SP>+</SP> regions 3b, bases constituted by P- regions 4n, and collectors constituted by N<SP>+</SP> regions 5b; the buried portion of 3b interconnecting the transistor emitters. (Fig. 3a). Transistors T 3 , T 4 comprise a N<SP>+</SP> collector region 6b, P- base regions 7b, and N<SP>+</SP> emitter regions 8b wherein the layer 6b interconnects the collectors. (Fig. 3b). N- channel MISFETS T5, T6 (Fig. 3a) are formed in N-type region 12b with drains constituted by collector regions 6b of transistors T 3 , T 4 and gates 11b being formed on insulant layer 11b. Sources are constituted by N<SP>+</SP> regions 9b in P- region 2b and the collectors of T 3 , T 4 and drains of T 5 , T 6 are interconnected. The emitters of T 1 , T 2 and the collectors and drains of T 3 , T 4 ; T 5 , T 6 are interconnected within the substrates and the remaining interconnections are established on the substrate surface to establish the circuit of Fig. 1. Since the collectors of inverse transistors T 1 , T 2 are connected by N<SP>+</SP> region the bases are constituted by low impurity P- regions, and the emitters by an N<SP>+</SP> layer; injection carrier efficiency and current gain are enhanced. The transistors T 1 , T 2 , T 3 , T 4 are NPN type in the P- layer and are thus selfisolating from the remaining elements respectively by their emitter and collector regions, and the interconnections within the substrate are in regions of high impurity concentration and low distributed resistance so that plural cells may be connected to word and power lines respectively. The depletion MISFET leads provide stable loading, high speed operation, and lower power consumption.
GB5677073A 1972-12-08 1973-12-07 Integrated semiconductor memories Expired GB1451084A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47122518A JPS4979793A (en) 1972-12-08 1972-12-08

Publications (1)

Publication Number Publication Date
GB1451084A true GB1451084A (en) 1976-09-29

Family

ID=14837823

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5677073A Expired GB1451084A (en) 1972-12-08 1973-12-07 Integrated semiconductor memories

Country Status (5)

Country Link
JP (1) JPS4979793A (en)
DE (1) DE2361172A1 (en)
FR (1) FR2210017B1 (en)
GB (1) GB1451084A (en)
NL (1) NL7316475A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2154086A (en) * 1983-12-26 1985-08-29 Hitachi Ltd Semiconductor integrated circuit device with power consumption reducing arrangement

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199478A (en) * 1975-02-28 1976-09-02 Hitachi Ltd HANDOTAISH USEKAIRO
JPS5325375A (en) * 1976-07-31 1978-03-09 Nippon Gakki Seizo Kk Semiconductor integrated circuit devi ce
KR950005463B1 (en) * 1992-06-29 1995-05-24 재단법인한국전자통신연구소 Emitter coupled logic semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2154086A (en) * 1983-12-26 1985-08-29 Hitachi Ltd Semiconductor integrated circuit device with power consumption reducing arrangement
US5111432A (en) * 1983-12-26 1992-05-05 Hitachi, Ltd. Semiconductor integrated circuit device with power consumption reducing arrangement

Also Published As

Publication number Publication date
FR2210017B1 (en) 1978-01-06
NL7316475A (en) 1974-06-11
JPS4979793A (en) 1974-08-01
FR2210017A1 (en) 1974-07-05
DE2361172A1 (en) 1974-06-12

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee