GB1446643A - Computer display terminals - Google Patents

Abstract

1446643 Display terminal COMPUTEK Inc 11 Sept 1973 42767/73 Heading G4A A display terminal includes a processor 18 (Fig. 2) receiving instructions from for example a keyboard for processing of data, the processed data being displayed on for example a CRT display, a common data bus being used for the instruction and display data in a time multiplexed manner (the single bus being shown as two separate buses 12, 14 in Fig. 2). An input/ output unit is provided as an interface between the terminal and peripheral devices such as a printer and tape cassette. As described, command signals are applied to source bus 12 from a keyboard or peripheral and processor bus operator 30 accepts data from the source bus, modifies it in accordance with instructions from micro-instruction decoder 36 and returns the processed data to the destination bus 14 for display. In each cycle there is a source and destination phase for the data bus, in the source phase a control signal SA indicating that the 5-bit address on the address bus represents the device which is to read data on to the bus and a control signal SR indicating that the processor is reading the data on the bus into a register and in the destination phase a control signal DA indicating that the 5-bit address represents a device which is to read data from the bus and a control signal DW generated by the processor indicating that the processed data is ready to be read. If, for example, a transfer instruction comprising 5 bits representing the destination address, 6 bits representing a modification and 5 bits representing the source address is extracted from firmware 74, a class of micro instruction decoder (64, Fig. 3, not shown) enables gating (68) to feed the source address bits to address bus drivers (66). When the source device places its output on the data bus, the bus register is loaded with data (possibly modified). In their destination phase address buffers (72) apply a destination address to drivers (66) and the selected device reads the data. If a literal load instruction is to be performed 5 bits represent the destination address, a particular bit is set to one (this being detected by the decoder (64)) and the remaining 10 bits represent data to be transmitted to the data bus. During the first phase no transmission occurs, the decoder enabling literal load gating (88) and destination gating during the destination phase. Skip logic increments the address for the firmware after each instruction. After a test instruction the address is incremented by 2 if the conditions are satisfied and by one otherwise to access a test wait instruction which is repeated until the test conditions are satisfied. Micro programmes may be provided to move a cursor on the cathode-ray tube display right, left, up or down and to insert or delete characters of the cursor position. Lines of displayed data may also be erased or rolled up or down and pages may be erased, with or without protected data.