GB1433003A - Pcm tdm telecommunications systems - Google Patents

Abstract

1433003 Automatic exchange systems SIEMENS AG 9 Aug 1973 [11 Aug 1972] 37822/73 Addition to 1402506 Heading H4K In a PCM, TDM system wherein a data transmission may be divided among several time slots in the same frame at the transmitting end, a number of different sections of an exchange are coupled to a 4-wire TDM highway via crosspoint switches and each section is connected to the switches via an outgoing intermediate store/buffer store arrangement operating in the manner described in the parent Specification and serving to collate received information relating to a data transmission according to the frame in which it was transmitted so as to compensate for the different frame delays incurred by the information in different time slots during the passage of the information through a multi-exchange system. The exchange has four sections 2KF, 4KF1-3 (section 4KF2 is not shown) and each section may be used for different types of transmission. Section 2KF is a two wire crosspoint switching network for speech connections which is coupled to an incoming/outgoing TDM highway An/Ab via crosspoint switches KS and a modulator/demodulator Mo/Dem. Sections 4KF1-3 are four wire crosspoint switching networks for data connections. one or more of which may be associated with video-phase connections and each section, e.g. 4KF1 is connected with the incoming highway An via an incoming intermediate store pair 1Sana, 1Sanb, a further store 01 and a crosspoint switch 1Kzb and is connected with the outgoing TDM highway Ab via outgoing intermediate store pair 1Saba, 1Sabb and a crosspoint 1Kza Under the control of addresses circulating in stores Ua, Ub information is read to and from the TDM highway An, Ab by the operation of the crosspoints KS, 1Kza-3Kza, and 1Kzb- 3Kzb, the function and operation of the buffer store 01-03 and the intermediate stores 1Sato 3Sa-being substantially as described in the parent Specification. The intermediate stores are shift registers having one storage location for each of a maximum of six time slots (only five locations being shown in the drawing) amongst which a data transmission may be divided in one frame and each storage location has a capacity of 8-bits. As different transmission rates require the use of differing numbers of time slots per frame it is necessary to provide a choice of clock frequencies via switches 1SchT-3SchT for stepping the shift registers. Further, although the inputs and outputs of the shift registers are shown as being at the first and final stages, where less than five times slots are to be used the input or output of the register may be shifted automatically to give a corresponding number of storage locations therebetween.