GB1428149A - Data transmission systems - Google Patents

Abstract

1428149 Data transmission; synchronizing of error correction systems STANDARD TELEPHONES & CABLES Ltd 2 Oct 1973 45883/73 Heading H4P In a synchronous duplex block coded error detection and correction system in which each block includes a portion acknowledging reception of a previously transmitted block from a second terminal which portion includes correct (OK) or request for retransmission (RQ), relative block phase in both directions of transmission is adjusted at one terminal only to maximize loop delay with which the system can operate satisfactorily. Initially, or for resynchronization, a continuous stream of sync. blocks each including (OK) is transmitted from a first terminal while the second terminal transmits a bit stream, reception of which enables bit sync. to be achieved. The sync. blocks on reception are monitored to establish sync. pattern for determination of block sync. which starts a decoder and parity checking means as a preliminary to processing data blocks; sync. blocks are then sent to the first terminal each containing (OK) or (RQ) dependent on parity check. The first terminal then monitors incoming blocks for block sync. which when obtained causes the first terminal to be switched to data transmission, followed by issue of data blocks. The circuit arrangement follows that disclosed in Specification 1,409,184 with certain modifications. Sync. and a start control 1 applies an enabling signal to S output lead and applies an inhibiting signal to cycle control 2 also a continuous OK to store 3. When sync. detector 4 detects that block sync. has been achieved, it sets distributer 5 in correct phase operation and control 1 is signalled; when it also receives OK from parity check unit 6 it removes inhibit from 2 and applies enabling polarity to St output for one block. This causes a "start of data block" signal to be transmitted followed by an enabling polarity on D output and hence transmission of data. At the remote B terminal, which differs from local A terminal, when sync. block detector recognizes the sync. pattern it starts an Rx timing distributer 5, also signals start control 1 which permits distributer 10 to cycle under the control of distributer 13 in the correct phase relative to received blocks. Inhibit from control 1 prevents unit 2 from cycling but condition of store 3 is determined by received blocks. Gate 21 is also enabled. Sync. blocks with RQ/OK bits of appropriate polarity are then transmitted. When St block, as detected by detector 4 and parity check 6, is received, this is signalled to control 1 which enables its St output causing a "start of data block" to be transmitted; this removes inhibit from unit 2 which can then perform retransmission cycles when required.