GB1421241A - Time-division multiplex data transmission - Google Patents

Abstract

1421241 Data transmission systems DATABIT Inc 4 Jan 1973 [6 Jan 1972 (3)] 596/73 Heading H4P A system for receiving data signals, including Telex signals, having two polarities, comprises: means for sampling the signals at predetermined intervals after receiving a signal having a first polarity representing a free line state, the sampling taking place after a lapse of time less than the interval between sampling pulses; means for inverting the polarity of the signals during a free line state; and means for restoring the polarity in response to a signal of predetermined length, whereby sampling is initiated by a transition in an inverted signal from the freeline polarity to the other and a Telex call signal having a length less than the sampling interval but greater than the time lapse is not missed. In an arrangement for time division multiplexing a 50 baud channel applied to interface 38, with a 75 baud channel applied to interface 40, clock signals are applied from time base 41 to the two interfaces, which are so programmed that the 50 baud data is sampled at a basic rate, and the 75 baud data is sampled at twice the basic rate. The sampled data and a " class of traffic " signal, indicative of which channel is being sampled, are fed to a synthesizer 42 which includes coding cards corresponding to the two baud speeds. The " class of traffic " signal selects an appropriate card, which causes a counter to count the samples, and generate a sampling pulse at the centre of the bit which is being sampled. This sample pulse is then stretched and fed to a bit counter 44 which contains further code cards corresponding to the two baud speeds. This counts the bits to determine the end of a character and, in the case of the 75 baud data, adds pulses after the second and fifth bits to convert it to 100 baud. The synthesizer 42 and counter 44 are coupled with a memory 50 and register 48 to regenerate the pulses and arrange them in the correct time slots. The data is then passed to the unit 59 which forms the frames and adds the synchronizing pulses. In order to accommodate calling pulses which are shorter than the normal data pulses, the bit counter 44 includes a unit which causes the synthesizer 42 to operate in the " invert " mode by time displacing the sampling pulses and shortening the bit counting period, which detects the end of a character, from seven bits to four. In this mode gates 92, 94 of the synthesizer, Fig. 4, from an alternative path for the signals IDB. The gates 96, 98 unlatch the adder stages A 0 ... A 5 after they receive their input.