GB1416959A - Digital computer organization - Google Patents

Abstract

1416959 Data processors GOODYEAR AEROSPACE CORP 14 June 1973 [12 July 1972] 28356/73 Heading G4A A digital computer includes an associative processor control memory having a number of separate memory units. Intermediate data and commands from the computer or elsewhere may be stored and accessed. Control programs are stored in the units. Segments of the programs are transferred between the units by a pager. A logic network (port logic) allows access to the units on a preset priority basis. A processor control network controls the manipulation of data in associative arrays in response to the programs. There are several such arrays operable in parallel, and each can access and operate on data in the array in bit-oriented and wordoriented mode. The embodiment described, Fig. 1, has three memory units forming the control memory 18. One unit is formed as a core store for the control programs. The other two units are solid state. One is a high-speed buffer. The other is organized as three pages, one of which contains frequently-used micro-programs. One of the other two pages provides instructions while the other is being loaded by pager 24 from the core store, and vice versa. Under control of port logic 26 a memory unit can be connected to allow control unit 16 to read an instruction from it, to control unit 20 for reading an instruction, or to the pager to load a new page. The processor control network 16 (and Fig. 3, not shown) receives from memory 18 commands to be executed immediately. It includes counters designating the field relevant to the operation indicated by the command and also designating the number of cycles pertinent to a loop command. Network 16 selects the required associative array 12, determines its mode of operation, and controls the apllication of masks and the shifting of data within the array. Each array includes a solid state 2<SP>n</SP> Î 2<SP>n</SP> bit matrix and an associated unit which operates in bitoriented or word-oriented mode to perform parallel logic or arithmetic on data in the array. Each mode uses the same read-write lines and the same arithmetic/logic unit. A permutation network in the array arranges the order of data to or from the matrix. Application to radar is mentioned.