GB1402927A - Monolithic memory system - Google Patents

Monolithic memory system

Info

Publication number
GB1402927A
GB1402927A GB5045572A GB5045572A GB1402927A GB 1402927 A GB1402927 A GB 1402927A GB 5045572 A GB5045572 A GB 5045572A GB 5045572 A GB5045572 A GB 5045572A GB 1402927 A GB1402927 A GB 1402927A
Authority
GB
United Kingdom
Prior art keywords
inactive state
driver transistors
transistor
driver
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5045572A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19712155802 external-priority patent/DE2155802C3/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1402927A publication Critical patent/GB1402927A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4116Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)

Abstract

1402927 Transistor memory matrix INTERNATIONAL BUSINESS MACHINES CORP 2 Nov 1972 [10 Nov 1971] 50455/72 Addition to 1334307 Heading G4C The integrated circuit memory of the parent Specification 1,334,307 is modified in that the gating means comprises, for each row, a driver transistor whose base is connected to a plurality of diodes in parallel which, in the inactive state, are reversed biased, there being a diverter circuit connected to the base of the driver transistors to prevent current flow through the driver transistors due to leakage currents in the reverse biased diodes. The description is similar to that of the parent Specification 1,344,307 except that a resistor R26 is provided to divert any leakage current flowing through transistors T101-T116, which, in the inactive state, form four parallel reverse biased diodes, away from driver transistors T20. The arrangement reduces power dissipation in the driver transistors in the inactive state. The resistor R26, which may be replaced by a transistor which is conductive when the chip is in the inactive state and non-conductive otherwise is common to all memory cell rows on a chip.
GB5045572A 1971-11-10 1972-11-02 Monolithic memory system Expired GB1402927A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712155802 DE2155802C3 (en) 1971-11-10 Monolithically integrated storage array

Publications (1)

Publication Number Publication Date
GB1402927A true GB1402927A (en) 1975-08-13

Family

ID=5824694

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5045572A Expired GB1402927A (en) 1971-11-10 1972-11-02 Monolithic memory system

Country Status (4)

Country Link
JP (1) JPS5238701B2 (en)
FR (1) FR2159534B2 (en)
GB (1) GB1402927A (en)
IT (1) IT1012520B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831673B2 (en) * 1979-08-22 1983-07-07 富士通株式会社 semiconductor storage device
JP2021507145A (en) 2017-12-14 2021-02-22 ペルマステーリサ エス.ピー.エイ. Dynamic vibration damping system for high-rise buildings

Also Published As

Publication number Publication date
FR2159534B2 (en) 1975-03-28
DE2155802B2 (en) 1975-12-18
JPS4857556A (en) 1973-08-13
DE2155802A1 (en) 1973-05-17
FR2159534A2 (en) 1973-06-22
JPS5238701B2 (en) 1977-09-30
IT1012520B (en) 1977-03-10

Similar Documents

Publication Publication Date Title
US3218613A (en) Information storage devices
GB1253763A (en) Improvements in and relating to monolithic semiconductor data storage cells
GB1236402A (en) Improvements relating to a semiconductor integrated circuit
GB1109820A (en) Multiple level logic circuitry
US3097307A (en) Opposite conducting type transistor control circuits
US2992409A (en) Transistor selection array and drive system
GB1174455A (en) Solid State Light Emitting Display with Memory.
GB1063003A (en) Improvements in bistable device
US3801965A (en) Write suppression in bipolar transistor memory cells
US2917727A (en) Electrical apparatus
US3192510A (en) Gated diode selection drive system
GB1402927A (en) Monolithic memory system
US3474262A (en) N-state control circuit
GB1292355A (en) Digital data storage circuits using transistors
GB1118054A (en) Computer memory circuits
US3210741A (en) Drive circuit for magnetic elements
CA1092239A (en) Shottky bipolar two-port ram cell
GB1036233A (en) Improvements in arrangements for performing logical operations
US3784976A (en) Monolithic array error detection system
US3655999A (en) Shift register
GB1122502A (en) Improvements in or relating to transistor switching circuits
US3703711A (en) Memory cell with voltage limiting at transistor control terminals
US3671946A (en) Binary storage circuit arrangement
GB1053834A (en)
CA1167961A (en) Non-dissipative memory system

Legal Events

Date Code Title Description
PS Patent sealed