GB1397710A - Logic circuit arrangements using insulated-gate fieldeffect transistors - Google Patents

Abstract

1397710 Semi-conductor logic circuits TOKYO SHIBAURA ELECTRIC CO Ltd 28 Sept 1973 [30 Sept 1972 11 Nov 1972] 45519/73 Heading H3T A clocked F.E.T. logic circuit 10, Fig. 1, has its output level at 17 maintained at a definite 1 or 0 level by a feedback circuit 40. The output appears on capacitor C L which is charged in # time by V ss and F.E.T. 13 and discharged or not by T14, T15 depending upon A, B. Leakage across C L and charge-sharing with stray C o affects the output level, and the circuit 40 corrects this by two stages of inversion T23, T24 and T34, T35 during ## time, ## acting on T33, T36. T14, T15 in logic circuit 10 thus perform a NAND function, but may be alternatively part of a so-called read-only array of F.E.T. storage devices (Figs. 9, 12, not shown). T35, T35 in the second inverter may be omitted (Fig. 3, not shown) and instead of clocking either of the inverter stages themselves, a clocked series-gate may be incorporated (T52, T53, Fig. 4, not shown). The conductivity types and voltage polarities may be reversed (Fig. 5, not shown); and the circuits may be adapted to use only single conductivity type F.E.T.s (Figs. 10, 11, not shown) wherein a threshold-boosting pull-up capacitor (261) may be incorporated. The clock pulses (#1 Fig. 8, not shown) which activate the feedback circuit (Fig. 7, not shown), may have a delayed starting edge to permit the output (S) on C L , if slowed by circuit time constants, to reach a distinct level before the feedback operates.