GB1393576A - Data transmission system - Google Patents

Abstract

1393576 Digital transmission; synchronizing INTERNATIONAL STANDARD ELECTRIC CORP 26 Oct 1972 49454/72 Heading H4P A receiver keeps in synchronism with a signal received in error-protected code by resetting its local clock-controlled counter BC when it thinks it detects a change from one received code word to the next. The local clock consists of a divider DIV producing a pulse CL1 (at the bit rate of the received signal), every 64th pulse CL3 from an oscillator OSC. CL1 controls the 31-bit counter BC to be reset in sync with each received 31-bit code word, which is set up in register IR. Supposing IR to contain a single complete 31-bit code word, the composition thereof is as follows: start and stop bits 0, 30 (1, 0); function bits 1-3 plus a parity bit 4; a six-bit address 5-10; information 11-23; and a code 24-29 added to produce a code word in cyclic code such as Williard or Barker code wherein a polynomial mod-2 division of the complete code word always gives a constant remainder (001011), which is checked at the receiver by a register DR. Three checks are made on the received code word by AND gate A11. Firstly, AND gate A3 enables one input of A11 if the start and stop bits 0, 30 and a parity check at PC2 on bits 1-4 are correct. A3 also initiates a logic sequence through A4-FN-A5-FM-A6 to enable A7. Secondly, A7 then causes fast recirculation through 08 and 01 of the contents of IR (at CL3 rate), and simultaneous division thereof in DR to check the remainder at A9, which enables a second input of A11 if the remainder is correct. Thirdly, AND gate A2 responds to bit 26 and a parity check at PCl on 27-30, to set FA and enable a third input of A11. If counter BC reached its total count at the same time as the first checked code word filled the register IR, then FP enables the final input of A11 and this causes A14 to transfer the received code word from IR to output register OR, synchronism having been confirmed. If, however, BC had not reached a full count, FP enables instead AND gate A12 which responds also to the remainder check from A9, and to a 0-to-1 transition in the receiver input line TC indicating a possible start of a new code word. If a repeat of the above three check process again succeeds, meaning that almost certainly two successive code words have been received, a logic sequence follows involving A12-03-FT-A21 -FC-A18 which resets counter BC to 0 and synchronizes it to the received code words.