GB1390034A - Semiconductor information storage devices - Google Patents
Semiconductor information storage devicesInfo
- Publication number
- GB1390034A GB1390034A GB4426371A GB4426371A GB1390034A GB 1390034 A GB1390034 A GB 1390034A GB 4426371 A GB4426371 A GB 4426371A GB 4426371 A GB4426371 A GB 4426371A GB 1390034 A GB1390034 A GB 1390034A
- Authority
- GB
- United Kingdom
- Prior art keywords
- read
- write
- circuit
- select line
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/4067—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the bipolar type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
Abstract
1390034 Transistor data storage circuits FERRANTI Ltd 21 Sept 1972 [22 Sept 1971] 44263/71 Heading H3T [Also in Division H1] Data digits to be stored on capacitance 21 are fed to it through a reverse-conducting bipolar transistor 18, and they then determine the conductivity condition of a junction FET 20 during read-out-to-write, a write select line 14 goes high when all inputs to circuit 11 (details Fig. 2, not shown) are high, and enables transistor 18 to charge C21 to a high level by reverse conductions if a high level exists on write line 16, or to a low level by forward conduction if a low level exists on 16. The P-channel junction FET 20 conducts only if no charge is stored on C20, and this condition is detected by earthing the read select line 15 (by T31, Fig. 2, not shown) and producing current flow from the read circuit 13 (details, Fig. 4, not shown). Such current flow (through T41, T40) turns off an output transistor (46) in the read circuit to give a high output at G. The high potential on write select line 14 is produced by the same set of allhigh inputs A-E as produce the low potential on read-select line 15, but after a delay determined by a diode D1 to allow for completion of read out. The write circuit 12 (details, Fig. 3, not shown) responds to either new information F, or to the feed-back output G of the read circuit for refreshing purposes.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4426371A GB1390034A (en) | 1971-09-22 | 1971-09-22 | Semiconductor information storage devices |
DE19722246331 DE2246331A1 (en) | 1971-09-22 | 1972-09-21 | SEMICONDUCTOR STORAGE |
JP47094723A JPS4840343A (en) | 1971-09-22 | 1972-09-22 | |
BR660472A BR7206604D0 (en) | 1971-09-22 | 1972-09-25 | A DATA PROCESSING DEVICE WITH A SEMICONDUCTOR DEVICE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4426371A GB1390034A (en) | 1971-09-22 | 1971-09-22 | Semiconductor information storage devices |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1390034A true GB1390034A (en) | 1975-04-09 |
Family
ID=10432499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4426371A Expired GB1390034A (en) | 1971-09-22 | 1971-09-22 | Semiconductor information storage devices |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS4840343A (en) |
BR (1) | BR7206604D0 (en) |
DE (1) | DE2246331A1 (en) |
GB (1) | GB1390034A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4209795A (en) * | 1976-12-06 | 1980-06-24 | Nippon Gakki Seizo Kabushiki Kaisha | Jsit-type field effect transistor with deep level channel doping |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2460150C2 (en) * | 1974-12-19 | 1984-07-12 | Ibm Deutschland Gmbh, 7000 Stuttgart | Storage arrangement that can be monolithically integrated |
DE2820321A1 (en) * | 1978-05-10 | 1979-11-15 | Hoechst Ag | METHOD OF MANUFACTURING MONOARYLTHIOURA |
DE3824694A1 (en) * | 1988-07-20 | 1990-02-01 | Fraunhofer Ges Forschung | SEMICONDUCTOR CIRCUIT FOR FAST SWITCHING PROCESSES |
-
1971
- 1971-09-22 GB GB4426371A patent/GB1390034A/en not_active Expired
-
1972
- 1972-09-21 DE DE19722246331 patent/DE2246331A1/en active Pending
- 1972-09-22 JP JP47094723A patent/JPS4840343A/ja active Pending
- 1972-09-25 BR BR660472A patent/BR7206604D0/en unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4209795A (en) * | 1976-12-06 | 1980-06-24 | Nippon Gakki Seizo Kabushiki Kaisha | Jsit-type field effect transistor with deep level channel doping |
Also Published As
Publication number | Publication date |
---|---|
DE2246331A1 (en) | 1973-03-29 |
BR7206604D0 (en) | 1973-08-30 |
JPS4840343A (en) | 1973-06-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |