GB1385455A - Integrating type analogue-digital converter - Google Patents

Abstract

1385455 Analogue to digital converter TEKELEC AIRTRONIC 27 April 1973 [1 May 1972] 20048/73 Heading G4H In a dual romp analogue to digital converter in which the unknown voltage is integrated for a period T 1 and a reference voltage is then applied for a period T 2 to reduce the integrated voltage to a second threshold voltage, the period T 1 is divided into A subperiods and the reference voltage is also applied to the integrator input during each subperiod that the integrated voltage at the beginning thereof exceeds a first threshold voltage. Clock pulses are fed to a counter whenever the reference voltage is applied to the integrator. The reference voltage is of opposite polarity to the unknown voltage and of a magnitude such that the integrator output is never less than zero. As described, the unknown voltage E x1 is applied as a current I 1 through AND gate 14 and OR gate 16 to integrator 18. The integrator output voltage is applied to comparator 50 which produces an output at A when E c exceeds a first threshold voltage E 1 and an output at B when E c is less than or equal to a second threshold E 2 . A reference voltage 8 in the form of current I 2 can be applied to the integrator by OR gate 16 and either AND gate 22 or 24 and also via OR gate 26 to enable gate 28 which passes clock pulses of frequency f 1 to counter 14B whose final count N 0 represents voltage E x1 . An oscillator 38 of PRF f 0 feeds a counter 34 of capacity N 1 which determines period T 1 and a second counter 36 of capacity N A = (N 1 )/(A) which determines each subperiod. Operation.-Operation of start circuit 40 starts oscillator 38 and feeds pulses of frequency f 0 to counters 34 and 36. The output #N 1 of counter 34 is inverted at 54 and enables gate 14 feeding current I 1 to the integrator. At the end of the first subperiod a signal N A is generated by counter 36 (which recycles) and is fed to AND gates 44 and 46. If there is a signal at comparator output A, flip-flop 48 is set and gate 22 enabled to pass reference current I 2 to the integrator and pulses of frequency f 1 to counter 32. If there is no signal at A, flip-flop 48 is reset via gate 46 and inverter 52. This is repeated at the end of each subcycle, the resetting of flip-flop 48 stopping current I 2 if it is flowing. At the end of period T 1 when a count N 1 is reached in counter 34, the output N 1 stops. Current I 1 via inverter 54 and gate 14, resets counter 34, stops oscillator 38 and sets flip-flop 42 which enables gate 24 to supply current I2 to the integrator and pulses of frequency f 1 to counter 14B. The count and current stop when a signal is generated at B on threshold circuit 50 signifying that E c is less than or equal to the second threshold voltage. This signal resets flip-flop 42. In alternative embodiments the ratio of f 1 to f 0 may be controlled or varied during the conversion so that it is non-linear. Other arrangements of counters are also described.