GB1385040A - System for converting modulated signals to squarewave outputs - Google Patents

Abstract

1385040 Optical reader BENDIX CORP 30 Nov 1972 [13 Dec 1971] 55365/72 Heading G4M [Also in Division H3] A system for shaping binary signals derived from energy reflected from a coded label comprises means for limiting one of the binary levels followed by means for thresholding the signals at the mid-level of the two binary levels. As described the pulses are derived by optical scanning of coding lines on a container passing on a conveyer belt. Laser light is scanned by an octagonal mirror (Fig. 1, not shown) and picked up on a photo multiplier tube, the first part of the scanning covering a reference label to produce control signals. The automatic thresholding circuit for the signals is preceded by the level setter, a first automatic gain control circuit controlled by the signal before thresholding and a second gain control circuit controlled before and during scanning and dependent upon whether a valid signal has been received. In Fig. 3 the output of the photo-multiplier tube is passed through an amplifier 36 to a black level clamping or limiting diode 41 which receives at its terminal 42 either a reference voltage determined by the black level of the reference level or arranged to follow the dark level of the signal. A timing pulse closes an FET switch 44 during the white level to correspondingly charge a capacitor 48 and the output of this is used as an automatic gain control signal for controlling an FET connected to the input of the amplifier. The gain controlled signal is applied to positive and negative peak level detectors 49, 54 and 51, 59. The mean of these levels is determined by a circuit 64 and applied as the threshold level to a thresholding amplifier 66 to which the gain controlled signals are also applied. The thresholded output from amplifier 66 is applied through a pulse width discriminating circuit which sets and resets a flip-flop 73 at leading and trailing edges respectively of the pulses. The output of the flip-flop is differentiated at 76 and 77 and, via OR gates 57, 63, discharge the capacitor ready for the next pulse edge. The differentiated leading and trailing edge signals from 76 and 77 are jointly applied to a delayed switching circuit 79 which causes discharge of the capacitor after a time greater than the widest expected pulse, to prevent lockup. Separate delays could be provided for leading and trailing edges. In order to prevent discharge by interfering signals the thresholded signals from 66 are passed through a pulse width discriminator in which leading and trailing edges operate respective delayed switching circuits so that AND gates 71 and 72 provide outputs only if the input pulse exceeds the delay time. Between the gain control circuit 19-39 and the detector 43 of Fig. 3 there may be inserted a further gain control amplifier 86. This provides a number of gain settings (two as shown) controlled by a processor logic unit 93 which detects at the end of the first scan whether the right number of marks has been sent. If this proves to be negative the other gain setting is selected and control by this channel is held by a flip-flop 94 until the end of the label. However, a measuring circuit 96 detects too high or too low a level during the scan and can readjust the gain accordingly. The correct measuring points are determined by a timing circuit (Fig. 9). A first timing counter starts at the commencement of the scan and provides an output from which is subtracted in adder 101 a number of pulses corresponding to the reference label width. If the first scan is determined as valid the gain lock flip-flop opens an AND gate 99 and the next scan is timed in a counter 98 and compared at 103 with the first scan and this provides a signal indicating that the level measurement in circuit 96 will be valid. Timing pulses T10, T20, T30, T40 indicating respectively that detection has started, that the dark level may be sampled, that the light level may be sampled and that the end of the scan has been reached so that both peak level store capacitors must be discharged are generated by a series of monostable crcuits (Fig. 8, not shown).