GB1366833A - Telemunications systems - Google Patents

Abstract

1366833 Digital transmission; error correction POST OFFICE 26 Jan 1973 4047/73 Heading H4P An encoding/decoding arrangement for error detection in a cyclic code, comprises: means 51 for partitioning a data word into a number of partitioned words; a check bit generator 59 and register 52 with the output of each connected to the input of the other; a modulo-2 adder 56 having one input connected to the means 51 and the other connected to the output of register 52; and means 53, 62 for determining when the register contains only zeros. The arrangement is one in which the encoded data is exactly divisible by a polynomial, so that any remainder detected after performing the division in the receiver will produce an error signal which can initiate a repeat. Encoding.-To encode a 32 bit message, the data is first recorded as four 8-bit words in memory 51. The most significant word is then fed from the memory via register 53, gate 54, adder 56 switch S2 (in the a position) to register 52. Switch S2 is then switched to the b position by a read only memory (Fig. 6, not shown) and the word stored in register 52 is fed via gate 58 to a check bit generator 59 which produces an 8 bit check signal which corresponds to the remainder when the 8 bit word is divided by the selected polynomial. This check signal is then fed to register 52. Switch S2 is again returned to the a position and the next word from memory 51 and the remainder signal from register 52 are added in modulo-2 adder 56, and the result fed to register 52 again. Switch S2 is again returned to the b position and the word now stored in register 52 is fed to check bit generator 59 to produce a new check signal which is again stored in register 52. The procedure is then repeated for the other two words stored in memory 51, to give a final check signal (the complete remainder) in register 52. This signal is fed to a further position in memory 51, and the complete message of 32 data bits and 8 check bits is read out over line 61. Decoding.-Similar apparatus is provided at the receiving station, the received message being written into a memory 51 as before. After performing the previously described operations on the whole signal (data plus check bits) the resulting remainder in register 52 is compared in comparater 62 with an eight zero bit signal derived from the read out memory via register 53. If the remainder in register 52 is also eight zero bits, indicating a correct transmission, the data signal is read out of memory 51. If the remainder is not eight zero bits, comparator 62 sends a "repeat" signal back to the transmitter. Details of a check bit generator for division by a polynomial X<SP>8</SP> + X<SP>2</SP> + X + 1 using EXCLUSIVE-OR gates are given in Fig. 4 (not shown).