GB1364742A - Code communication system - Google Patents

Abstract

1364742 Selective signalling EDWARDS CO Inc 19 June 1972 [24 June 1971] 28618/72 Heading G4H In a communication system with a central station and remote stations, the central station responds to a start signal from a remote station to send a search code in an operation cycle, reception at the remote station of a search code bit unequal to the corresponding bit of the remote station address causing the central station to terminate the cycle and start a further cycle in which the search code is sentagain but with the last search code bit sent in the previous cycle inverted in value. In response to the start signal, a 16-bit address and data register in the central station has its 10-bit address section set to all ones to constitute the search code which is then serialized under control of a clock-driven counter and sent to the remote stations. (The other 6 bits are used for controlling devices at a remote station). At a remote station, a clock train derived from the received signal drives a counter to serialize the station address from a store for bit-by-bit comparison with the search code. Detection of inequality at any bit position resets the counter and, if the remote station was sending a start signal, cuts this off. The central station may still be receiving a start signal from one or more other remote stations but when all the start signals have been cut off the central station (as stated above) stops its cycle, inverts the last bit sent in the address and data register, and starts a new cycle in which the modified search code sent. Thus, the search code is progressively modified to equal the address of the station sending a start signal (or the highest-address station of those sending a start signal) which is then selected in that when the counter has counted to 10 without being reset, i.e. the 10-bit search code equals the station address, the 6 data bits from a "controlled devices and monitor code selector" block are serialized under control of counts 11-16 of the counter and sent to the central station. The counter then continues to count from 1 upwards again to send the station address to the central station. At the central station, the 6 data bits and the address are placed in another 16-bits address and data register. The address is compared with the search code in the first address and data register as a check. If equal, and if a dual bit detector fed from the line from the remote stations is not producing an output, a decoder is enabled to control indicators for the remote stations from the second address and data register. The above mode of station selection is initiated by a change of status in the "controlled devices and monitor code selector" block in a remote station, which produces the start pulse to initiate the above mode at the end of the current cycle, but normally the central station selects the remote stations in numerical address order, one per cycle, by loading the address section of the first address and data register from a station counter, the address being serialized and transmitted like the search code above, each remote station other than that addressed resetting its counter at the first inequality between its address and that transmitted, the addressed station sending its data and address back as before. The station counter is normally advanced once each cycle, but if the address check comparison at the central station or the dual bit detector indicates error, the same address is sent in the next cycle. If the error persists, the address in the first address and data register is saved in storage and displayed and an alarm is given. The station counter is then advanced whether the error persisted or not. Three D.C. channels link all the remote stations to the central station in common, for transmission in the two directions and for the central station to send a reset signal to the remote stations at the end of each cycle, respectively. Different frequencies on a single line can be used instead.