1355695 Digital measurement COLT INDUSTRIES OPERATING CORP 15 Oct 1971 48056/71 Heading G4H Electronic measuring apparatus includes means for deriving a first electrical signal representing a quantity measured by measuring apparatus, storage means for storing this electrical signal and comparison means for comparing the electrical with a second signal subsequently derived from the measuring apparatus to obtain a further electrical signal representative of the algebraic difference between the two outputs from the measuring apparatus. As described the first signal is derived when the apparatus is in a zero set mode and the second signal is derived when the apparatus is in a non-zero set mode. General operation.-Each of the modes lasts for forty clock pulses and is controlled by a clock control comprising a units clock 192 and a tens clock 194 (Fig. 2). To initiate a zero set mode, button 42 is operated to set zero set latch 40. This results in a bare value set upon switches 106 being read in to binary coded decimal counters 94a-94d during clock pulses 0-9. Between the ninth and tenth clock pulses the clock rate is slowed and the measuring circuit 22 is brought into operation so that during each of the clock pulses 10-19 the input is digitized by accumulating pulses, for a time interval the length of which depends on the input signal to the measuring means, in counters 94a-94e. During clock pulses 20-29 the measured count is stored in complementary form in memories 120a-120e and during clock pulses 30-39 the zero set latch 38 is released. In a non-zero set mode during clock pulses 0-9 the number stored in the counter complementary memories 120a-120e is entered back into the counters 94a-94e so that during the digitizing period the counter counts up from this value. At the end of clock pulse 19 the most significant digit in the highest decade counter 94a is sensed and if it has changed from 9 to 0 the number in the counter is directly read out. Otherwise the complement of a count is read out. At this time a number detector 26 operates a rounding-up function by causing the counter to be pulsed until the least significant digit in counter 94d is 0 or 5. The count is subsequently read out to memories 118a-118e connected to decoders 132a-132e and displays 134a-134e. The apparatus may be used in a weighing system in which it is required to obtain the weights of individual packages as they are added to a partially loaded pallet without removing the pallets from the weight platform for each measurement. This is achieved by using the zero set button to rezero the system at the addition of each package so that the weight of the added package only is displayed. Measuring unit.-The measurement unit is an analogue/digital converter in which the input signal is compared with ramp signals. The input signal 44 is derived from a plurality of load cells 48 and fed to a D.C. amplifier 52. An A.C. amplifier 56 phase shifts by 180 degrees any A.C. components in the signal, its output being recombined with the output of the D.C. amplifier 52 to reduce any A.C. components in the analogue signal. A negative bias from source 64 and positive going ramp signal from generator 68 are combined with the D.C. signal, the resultant signal being applied to a zero crossing detector 62 which when triggered enables a gate 72 (primed at clock pulse 10 by the setting of a bistable 84) to supply pulses from crystal controlled oscillator 74 to the lowest stage 94e of the decade counter. The output of a ramp generator 68 is also compared with a negative signal from a bias source 76 to control a second zero crossing detector 80 which when triggered resets the bi-stable 84 to close the gate 72 and to terminate the generation of the ramp. This process is repeated during each of the clock pulses 10-19. Clock control.-After a control bi-stable (16, Fig. 6, not shown) is switched a capacitor (246) charges and discharges by the action of a unijunction transistor (258) so that the units count 192 in the clock control is advanced. At a count of ten the resulting signal from the lowest stage of the tens counter results in a signal being applied to decrease the clock-pulse speed for the measurement cycle. At a count of 20 this signal changes state resulting in the clock pulse frequency reverting to its faster rate. At this time in the zero set mode the counter complementary memories 120a-120e are pulsed so that the contents of counters 112a-112e are read in. In the non-zero set mode 130a-130e are enabled at this time so that the counts are entered into memories 118a-118e for decoding to decimal form and displaying. When the complement of the count is displayed a minus indicator is operated. Rounding up.-If at the end of the nineteenth clock pulse counter 94d is at zero all the outputs 122 of counter 112d will be at zero. This results in a zero signal to memory 200 so that via gate 88 the ramp control bi-stable 84 is reset to stop the supply of pulses to the counter 94e. If however the count in counter 94d is not already rounded up the bi-stable 84 is not reset but a new ramp is initiated with pulses continuing to be fed to the counter until a 0 or a 5 is detected therein when the resulting zero signal operates the memory 200. Complementer.-When the value of the most significant digit does not change between its value at the tenth clock pulse (that is the value of the number stored in the complementary memory) and its value at the twentieth clock pulse (that is the value after the measurement) a complementer (Fig. 4, not shown) comprising inverters and exclusive OR gates derives the nines complement of each decimal digit. This is achieved by performing the operation A<SP>1</SP> = A, B<SP>1</SP> = B, C<SP>1</SP> = C.B + B.C and D<SP>1</SP> = B.C.D where A, B, C and D are the binary bits of the stored count and A<SP>1</SP>, B<SP>1</SP>, C<SP>1</SP>, D<SP>1</SP> are the outputs fed to the decoder for display. Automatic zero control.-When the count in the counters 112a-112e at the twentieth clock pulse is within a predetermined band around zero, e.g. if it is 00039, circuitry (Fig. 11, not shown) comprising inverters connected to selected outputs of the counters 112a-112d detects this low value and derives a signal to operate the zero set latch 38 in the same manner as occurs when the zero set button 42 is operated in the zero set mode. More than one such unit may be included so that different bands may be detected.