GB1350800A - Data transmission - Google Patents

Abstract

1350800 Digital transmission; closed loop systems WESTERN ELECTRIC CO Inc 7 Oct 1971 [8 Oct 1970 (2)] 46680/71 Heading H4P A digital transmission system has a plurality of closed loops each including a number of stations B entering message blocks thereon, and a plurality of switching stations C for selectively transferring messages in accordance with the address between adjacent loops. Loops are normally closed by an A station which selectively repeats transmissions and preferably prevents continuous recycling. Loops need not be synchronous but it is preferable that the A stations provide timing and that this should be by way of a carrier wave. Due to buffering at the C stations adjacent loops need not be precisely synchronized. Error control may be incorporated, but supervision may be provided, for example, over a telephone network. A trunk loop i.e. 10 not incorporating access facilities may connect subsidiary loops. By-pass i.e. alternative transmission paths may be provided either to divert traffic from heavily laden or faulty sections and some loops may be duplicated. Message blocks may include reserved bit positions and each station includes a shift register in series with a loop for serially accepting and entering data from and to the loop with parallel data access means also detection means to prevent insertion in "loop busy conditions". "Hog" circuits may also be incorporated to prevent stations having continuous access to the detriment of other stations having messages for transmission. A station B may comprise a demodulator and amplifier (52) Fig. 3 (not shown) together with a clock pulse recovery and synchronizing circuit (53) for the generator (55). Demodulator output is received by a shift register (54), see also Fig. 5 (not shown) which is a serial input serial output nine stage register having parallel access to all stages which are made available to control circuits (56) which detects the sync. code, block control word also destination code, see Figs. 7-10 (not shown), the output controlling in turn write and read circuits (59, 62) which operate in conjunction with overflow eight stage register 58 having parallel reading and writing access. Thus single message blocks may be received by register 58 or entered through 65 which may insert guard bits also interchange source and destination codes to return undelivered messages to a sender. B stations may be modified for A station use by providing, for example, a master timing generator, eliminating read and write circuits (62, 59) but a circuit (66) see Fig. 14 (not shown) must be provided to initialize the loop when block framing is lost which may be accomplished by inserting nine zeros followed by a series of 1's. C stations may comprise two B stations (600, 601) Fig. 15 (not shown) each coupled into one loop, which deliver into and receive from stores (603, 604) all controlled at (605). A B station, e.g. (600) may retransmit messages on the same loop, e.g. (1) or in response to "foreign" addresses may be transferred to the other B station for insertion on to loop (2). To prevent message blocks being lost, the size of stores is made large enough relative to anticipated amount of interloop traffic. Stations (600, 601) need not operate at the same repetition rate nor be in synchronism. Store units (603, 604) may each comprise a magnetic core matrix with associated X, Y selection circuits in accordance with address information from appropriate decoders (615, 616) Fig. 16 (not shown). Detailed arrangements for performing various operations are described in the Specification.