GB1340985A - Chrominance saturation control circuit - Google Patents

Abstract

1340985 Gain control; television MATSUSHITA ELECTRONICS CORP 24 Feb 1972 [5 March 1971 8 March 1971] 8594/72 Heading H4R A chrominance saturation control circuit comprises a first differential amplifier having two transistors 10, 11 a chrominance saturation control D.C. voltage being coupled, via terminal 9 to the base of one of the transistors, two current to voltage converting transistors 16, 17 connected to the respective collectors of the first transistors 10, 11, two emitter follower transistors 18, 19 connected to the respective emitters of the transistors 16, 17, and a second differential amplifier having two transistors 5, 6, the voltages on the emitters of the two emitter followers 18, 19 being differentially coupled to the second differential amplifier. A chrominance signal is coupled-in the embodiment, from terminal 1, via common transistor 2-to the emitters of the two transistors 5, 6, the collector of one transistor 6 being connected to an output terminal 8 at which a chrominance signal controlled by the D.C. voltage at terminal 9 appears. In the embodiment, a further differential amplifier comprising transistors 25, 26 is provided, also controlled from the emitter-followers 18, 19, the collectors of transistors 6, 26 being connected together so that the D.C. level in the output does not change as the D.C. voltage at terminal 9 changes. Transistors 22, 27 form common emitter loads for the differential amplifiers 10, 11 and 25, 26 respectively: the transistors 2, 22, 27 are provided with a fixed bias from terminal 32. According to the Specification the arrangement is of use other than in chrominance control circuits.