GB1337966A - Radar processing equipment for navigational and collision avoidance apparatus - Google Patents

Abstract

1337966 Pulse radar IOTRON CORP 1 Dec 1970 [15 Dec 1969] 57041/70 Heading H4D A radar processing equipment comprises a counter for target pulses from a defined range, means responsive to a predetermined maximum count, a computer responsive to said means and a display responsive to said computer wherein said computer causes said display to indicate targets of less than a predetermined size but not to indicate the major portions of targets greater than said size. Echoes are digitized in quantizer 24, Fig. 3, and fed to series connected delay lines 30, 32. Line 32 is also connected to a single register bit 34. Bits 36, 38, 34 are analysed and a content 100 therein signifies the beginning of a target at a particular range, thus causes bit 46 of the "target present" register to be set. Range gating is accomplished by parallel shifting of the information through the memory 26 at each clock pulse. Memory 26 consists of fourteen shift registers of length equivalent to the maximum range, plus a single bit 34. The registers are also cyclically connected such that information is retained over a number of transmitter pulses unless it is removed during a readout sequence. After a transmitter pulse the echo signals pass through the delay lines 30, 32, 34 and logic 28 determines from the content of bits 36, 38, 34 when a target echo is present. If so, counter 40 is incremented by one and counter 40 which is enabled by the target present signal counts the number of zeros in the target response. Thus the counter 40 measures the extent of a target in azimuth and counter 42 measures its viability. A detector (56, Fig. 4, not shown) analyses the echo signals in range and if a range extending target is found, the "target present" register is blanked out except for a pulse representing the leading edge of such a target. When logic 28 detects that the content of bits 36, 38, 34 is 001, this indicates the end of a target and logic 28 enables a comparator which measures whether the content of counter 40 at this range is (a) below a minimum value, (b) above a maximum value, (c) between (a) and (b). If (a) then counters 40, 42 and bits 52, 54 are reset to zero. If (b) bits 52, 54 are set to "1". If (c) then bit 54 alone is set to "1" if the content of counter 42 is low. At the end of the time period corresponding to maximum range counter 22 stops clock 20 and the read in cycle to memory 26 stops. The readout cycle then begins. Shift control 90, Fig. 6, shifts the memory registers until logic 82 detects a "1" in bit 54; logic 82 then detects the type of target from the content of bits 52, 46 i.e. 00 indicates a range extended target; 11 indicates an azimuth extended target; 01 indicates a normal target. The range and azimuth extension of the targets are then applied to computer (14) through gates 84, 86 and for a normal target the speed and direction thereof are also calculated. Range and azimuth extended targets are displayed directly, although due to the resetting of the target present register by the detector (56) only the leading edge of range extended targets is displayed. Counters 40, 42 and bits 52, 46, 54 are then reset to zero and the readout cycle continued.