GB1336780A - Integrated circuit and method of manufacturing same - Google Patents

Integrated circuit and method of manufacturing same

Info

Publication number
GB1336780A
GB1336780A GB4524671A GB4524671A GB1336780A GB 1336780 A GB1336780 A GB 1336780A GB 4524671 A GB4524671 A GB 4524671A GB 4524671 A GB4524671 A GB 4524671A GB 1336780 A GB1336780 A GB 1336780A
Authority
GB
United Kingdom
Prior art keywords
substrate
doped
region
oxide layer
zones
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4524671A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of GB1336780A publication Critical patent/GB1336780A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1336780 Semi-conductor devices THOMSONCSF 28 Sept 1971 [2 Oct 1970] 45246/71 Heading H1K An integrated S/C circuit (Figs. 1, 2) comprises an e.g. N doped Si wafer 1 covered with a layer 2 of Si, O 2 in which are formed a P + doped source region 3 with grounded metal contact 32, a P doped channel 7, and a N+ doped gate region 9 with metal contact 92 extending into a further area to form contact 10 wider than the plate, deposited on an exposed substrate zone 101 and overlapping the oxide layer. A P+ doped region 4 forms the drain region, with metal contact 42 and further contact 43 connected thereto extending over the oxide; and a P doped region 81 constitutes a load resistor extending from region 4 to a P + doped region 5 which with an inlet contact 52 forms a negative D.C. supply input. A substrate zone 111 overlapping the oxide layer with metal contact 11 overlying the oxide layer is connected to bias source, and the substrate between zones 101, 111 constitutes a bias resistor Rp; and an elementary amplifier circuit is thus formed (Fig. 3, not shown). In manufacture, the oxide layer is formed by cathode sputtering or wet thermal oxidation, and the necessary windows therein are etched through a resin mask apertured electronically by the modulated beam of an electron microscope under analogue or digital control of the mask configuration. P-Regions 3, 4, 5, 7, 8 are formed by ionic implantation of e.g. Bo; the regions 3, 4, 5 having a high P + concentration and regions 7, 8 having a lower P - concentration. The element is then thermally annealed, and oxide layer 2 is reconstituted by cathode sputtering in zones 3, 4, 5, 7, Rc. Further windows delimiting zones 9, 101, 111 are etched using an electronically apertured mask, and P doping is ionically implanted to obtain gate region 9 and the ohmic substrate contacts 101, 111 delimiting Rp. After further annealing, windows to zones 3, 4, 5 are etched through an electronically apertured mask to expose the substrate, Al is vapour deposited, and further electronic masking and etching delimits the integrated circuit connections and contacts while preserving regions 3, 32, 4, 5, 9, 52, 101 and 111. Schottky gates may be used instead of implanted gates, and the substrate may be other than Si. Individual components are isolated initially by the substrate.
GB4524671A 1970-10-02 1971-09-28 Integrated circuit and method of manufacturing same Expired GB1336780A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7035702A FR2108770B1 (en) 1970-10-02 1970-10-02

Publications (1)

Publication Number Publication Date
GB1336780A true GB1336780A (en) 1973-11-07

Family

ID=9062203

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4524671A Expired GB1336780A (en) 1970-10-02 1971-09-28 Integrated circuit and method of manufacturing same

Country Status (6)

Country Link
JP (1) JPS56110668U (en)
CA (1) CA955690A (en)
DE (1) DE2149154A1 (en)
FR (1) FR2108770B1 (en)
GB (1) GB1336780A (en)
NL (1) NL159816B (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4622043A (en) * 1978-06-19 1986-11-11 Rca Corporation Textile dyeing process: multicolor pattern dyeing of tufted nylon carpet

Also Published As

Publication number Publication date
FR2108770B1 (en) 1973-11-23
FR2108770A1 (en) 1972-05-26
NL7113236A (en) 1972-04-05
CA955690A (en) 1974-10-01
JPS56110668U (en) 1981-08-27
NL159816B (en) 1979-03-15
DE2149154A1 (en) 1972-04-06

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years