GB1335710A - Voter circuits for triple redundant systems - Google Patents

Abstract

1335710 Digital transmission ELLIOT BROS (LONDON) Ltd 15 Sept 1971 [15 Sept 1970] 44082/70 Heading H4P A three circuit redundancy system maintains separate outputs equal at a value which is a function of three input signals. Normal differences between channels do not simulate an error. The system includes transient suppression by means of a fader so that outputs of sync. circuitry do not exhibit step changes, hence larger disparities between inputs can be accommodated. In one embodiment a channel 2 is chosen as a reference and channels 1, 3 are synchronized to it hence failure of channels 1 or 3 have no effect on the output. On failure of channel 2 channel 3 is chosen as a reference, all other outputs being compared with this. Transients can arise from switching from channel 2 to 3 hence, on failure, a fader fed from these channels is switched temporarily to inject a signal into the sync. circuit, equal to and opposite the difference between channels 2, 3 which decays to zero. Signals in channel 2, before, and channel 3, after, changeover do not themselves pass through the fader. The fader circuit may be triplicated. The monitoring circuit consists of a first part for error detection, e.g. amplitude comparison, each fed for a pair of channels, which produce a signal when inputs differ by more than a determined amount. Outputs are combined in a logic circuit producing three error outputs 17, an output 18 indicating single channel failure, and 19 two channel failure. The second part is essentially a switching arrangement which connects three inputs to sync. circuit outputs. In normal operation the switches are in the position shown and all outputs are driven from respective inputs. Any difference between channels 1, 2 is detected by amplifier Al which has limited authority so that a failure does not cause disruption of more than one output. This amplifier also feeds amplifier 13 which as is responsive to the difference between channel 1 and channel 1 minus channel 2 its output is equal to the channel 2 input. Similarly amplifier 15 follows the channel 2 input. In the event of failure of channels 1 or 3, one of lines 17 will be energized hence changing the position of switch S1 resulting in amplifier 13 being driven from channel 2, or S3 resulting in channel 1 driving amplifiers 13, 15 and the difference between channels 1, 2 being subtracted from both. Either of these failures leaves output signals substantially unchanged. In the event of failure of channel 2 switches S2A, S2B, S2C are reversed hence channel 3 drives three outputs instead of channel 2. Additionally switches S2D, S2E changeover in fader circuit 20 which previously had been receiving an input from channels 2, 3 thus an amplifier A3 forms the difference between these channels which is stored in an integrator Il. On failure switch S2D opens and S2E is closed thus supplying the stored quantity to amplifiers 13-15 with the previous difference between the channel 2, 3 signals. The signal on the integrator will gradually decay to channel 3 level with time. In another arrangement, the average of inputs to channels 1, 3 is chosen as a reference value thus failure of channel 2 has no effect. On failure of channel 1 or 3 channel 2 is employed as a primary channel.