GB1331111A - Electrical circuits - Google Patents

Electrical circuits

Info

Publication number
GB1331111A
GB1331111A GB1331111DA GB1331111A GB 1331111 A GB1331111 A GB 1331111A GB 1331111D A GB1331111D A GB 1331111DA GB 1331111 A GB1331111 A GB 1331111A
Authority
GB
United Kingdom
Prior art keywords
circuit
output
mark
level
representative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Post Office
Original Assignee
Post Office
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Post Office filed Critical Post Office
Publication of GB1331111A publication Critical patent/GB1331111A/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/10Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/16Frequency regulation arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

1331111 Digital transmission; FSK systems; phase locking and detecting; detecting whether signal is within a given amplitude POST OFFICE 22 April 1971 [29 April 1970] 20534/70 Headings H3A H3T and H4P A circuit for comparing two input trains of pulses comprises responsive to the trains a bistable arrangement giving a mean output signal representative of the relative times of rest in each state. As applied to a F.S.K. system wherein marks and spaces are representative by plus and minus frequencies relative to a carrier, the mean signal causes adjustment of an oscillator automatic tuning circuit (VFO, Fig. 1, not shown) to the mid point between the mark and space received frequencies via a signal assessor (1) which comprises a pair of differentiating networks. The bi-stable circuit comprises transistors VT13, VT14 with separate inputs from mark and space trigger circuits (Fig. 3, not shown) connected to the bases. The bi-stable circuit output is connected to a circuit comprising a diode D7, capacitor C19 and resistor R38 producing an output representative of the bi-stable mark-space ratio, which is examined by detector 4. The upper and lower threshold detector comprises an emitter follower VT8 connected to a Schmitt trigger circuit including transistors VT9, VT10 with a potentiometer RV1 setting the trigger level. Separate outputs, connected through input circuits comprising Zener diodes D5, D6 and C.R. networks to series transistors VT11, V12 form an AND network giving the following effects:- D.C. level below lower threshold; VT11 ON, VT12 OFF, hence output equals "1" D.C. level between lower and upper thresholds; VT 11 ON, VT12 ON, hence output equals "0"; D.C. level above upper threshold; VT11 OFF, VT12 ON, hence output equals "1". The 1 and 0 signals start and stop the motordriven tuner to restore equality to the signals emitting from the demodulator (8). It is stated that a similar arrangement may be employed for phase difference indication between two waveforms of the same frequency.
GB1331111D 1970-04-29 1970-04-29 Electrical circuits Expired GB1331111A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2053470 1970-04-29

Publications (1)

Publication Number Publication Date
GB1331111A true GB1331111A (en) 1973-09-19

Family

ID=10147475

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1331111D Expired GB1331111A (en) 1970-04-29 1970-04-29 Electrical circuits

Country Status (1)

Country Link
GB (1) GB1331111A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2245442A (en) * 1990-06-20 1992-01-02 Mitsubishi Electric Corp Frequency error detecting apparatus
GB2332311A (en) * 1997-12-12 1999-06-16 Nec Corp AFC in FSK receiver

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2245442A (en) * 1990-06-20 1992-01-02 Mitsubishi Electric Corp Frequency error detecting apparatus
GB2245442B (en) * 1990-06-20 1994-06-01 Mitsubishi Electric Corp Frequency error detecting apparatus
GB2332311A (en) * 1997-12-12 1999-06-16 Nec Corp AFC in FSK receiver
GB2332311B (en) * 1997-12-12 2000-01-26 Nec Corp Automatic frequency control in FSK receiver
US6332007B1 (en) 1997-12-12 2001-12-18 Nec Corporation Automatic frequency control in FSK receiver using voltage window deviation

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees