GB1325414A - Circuit for delaying information in the form of analogue signals - Google Patents

Abstract

1325414 Active delay circuits; sonar and direction-finding systems FRIED KRUPP GmbH 24 March 1972 [25 March 1971] 13891/72 Headings H3U and H4D In an analogue delay circuit, signals to be delayed are connected to a first path comprising a threshold circuit 2 and a shift register 4 and a second path comprising an amplitude detector 7, the outputs from the shift register and detector being multiplied at 8 and then fed to an output filter 9. Sinusoidal input signals at 1 are converted to a rectangular waveform by threshold circuit 2, and corresponding delayed rectangular signals may be obtained from the outputs of one or more of the stages of shift register 4, the signal being stepped through the register by a clock signal on 5 whose frequency determines the delay per stage of the register. An output of the required delay is applied to one input of a multiplier 8 which may be a simple FET switch, Fig. 4b (not shown). The input at 1 is also fed to a conventional diode peak or mean level detector 7, the output from which is a D.C. whose level depends on that of the input at 1. The result of multiplying this signal with the shift register output is a delayed rectangular wave signal whose amplitude corresponds to that of the input signal, which is subsequently passed through a low-pass or band-pass filter 9 to reconvert it to sinusoidal form. The delay may be employed in a direction finding system, in which transducers for electromagnetic or acoustic waves are arranged in a circular or linear array, Figs. 5a, 7a, 7b (not shown). In one embodiment, Fig. 5b, the output from each transducer of a circular array W1... W8 is fed to a respective delay arrangement, each of which includes a number of multipliers 8W which receive inputs from different tapping points on the associated shift register 4W. The phase-shifted signals from each transducer thus obtained are appropriately combined in units 15 to provide a number of outputs 16a1 ... 16am each of which corresponds to a particular bearing from the array. The system may be switched from a receiving to a transmitting mode of operation by a suitable switching arrangement, Fig. 6 (not shown), which connects the transducers to the outputs instead of the inputs. In a modified arrangement, Fig. 7c (not shown), only one multiplier 8W is associated with each delay, and the output from each stage of the delay is fed to it in turn via a cyclic switching circuit (18). In a further modification, Fig. 9 (not shown) for a linear transducer array, each shift register 4W has a single output which is fed to its associated multiplier 8W, and the outputs of the multiplier are fed to a single combining circuit (15). The relative delays from each delay arrangement are varied by controlling the relative clock frequency generated by multiple clock generator 20. Switching from receive to transmit mode may be again provided, Fig. 10 (not shown).