GB1322246A - Interface for start-stop terminal with data network - Google Patents

Abstract

1322246 Telegraphy STANDARD TELEPHONES & CABLES Ltd 30 Sept 1971 [6 Oct 1970] 47460/70 Heading H4P An interface between a teleprinter terminal and a synchronous network provides a series of '1' pulses for a bit of one polarity and a series of '0' pulses for the other polarity with means to detect changes of bit type, and a counter to count 1's or 0's from each change. At least one pulse position is scanned in each sequence and data bits are formed from each group of pulses to form a character. Majority decision equipment may be employed operating on three or more correct samples. The pulse stream modulation equipment only may be located at a terminal while data processing apparatus, which can be time shared, can be located at a switching centre (DSC) or concentrator. In a basic embodiment the terminal operates with 7¢ bit start + 5 + stop code and interface issues 15 x 1's for each mark and 15 x 0's for space "free" time being indicated by continuous space. At a concentrator or DSC operating into a 10 bit character network start/ stop bits are detected and may be incorporated, or removed according to design. After sampling, elements are shifted into register TS-IN and when complete the character is transmitted; a reverse process operates through TS-OUT (see Fig. 1, not shown). Register TC-IN is divided into three sections, stages 7-10 receiving bit count and indicating sampling time, 4-6 element count for successive characters, which are subsequently transferred to a time shared common processing register. Incoming bits through flip-flop Bit-In are passed into stage 4; when the first bit arrives sections 4-6 and 7-10 are of TC-IN are started, 7-10 counting 15 bits then recommencing. Each count increments the element count. At bit count 7 the sample indicated is set and the current bit in Bit-In is shifted into TS-IN position 4. Each character from a terminal may be accumulated asynchronously. Receipt of a stop-bit may reset count in TC-IN An envelope transmission device examines each (assuming there is more in one) TS-IN sequentially, and if a complete character is available it is assembled into network envelope form with status and sync. bits if required and transmitted to DSC. If a character has not fully been accumulated an "empty" envelope is transmitted, either formation being placed in the register CHR. A "clear" terminal line is indicated by a long space and on detection of all spaces in TS-IN it is assumed tentatively that this represents a clear signal. A number of "clear" successive characters are recorded in positions 1-3 of TS-IN and at a determined count e.g. 3, further incrementing is stopped and a "clear" signal envelope is formed in CHR. Transmission may be delayed to ensure that a "clear" signal on the terminal line has not been generated spuriously. When not counting clear signals, stages 2, 3 of TS-IN may be used for majority decision counts on 6, 7 and 8 pulses, and when 8 is reached content of bit-in is shifted into stage 4. A bulk redundancy method for use with a 50 baud terminal and 750 bit/sec bit stream is described in connection with Fig. 3. In an alternative arrangement, not particularly described, start and stop bits may be removed at a concentrator on inward transmission from a terminal and inserted on outward transmission. A data character with erroneous stop character would leave the line incorrectly set to space since it is preferable for the equipment to be returned to mark after transmission of the seventh element. With a 110 baud transmission a regular strobing would give irregular off-centre samples hence a modified count may be used with double steps to provide correction. Two 10 bit words can provide control and storage for this speed and Fig. 4 (not shown) illustrates an embodiment whereby data bits can be accumulated in locations (LA, LB) with "shift over" by a bistable (SO); the DSC has access to both locations to obtain a complete character. Buffer (BA) smooths uneven flow of information. Fig. 5 (not shown), illustrates the use of two 10 bit registers (LC, LD) whereby count and data functions can accept succeeding character bits before clearance of a previous character bit on a circulatory basis. A method of establishing connections through the equipment is described in the Specification.