GB1311078A - Digital data signal detection circuits - Google Patents

Digital data signal detection circuits

Info

Publication number
GB1311078A
GB1311078A GB3985771A GB3985771A GB1311078A GB 1311078 A GB1311078 A GB 1311078A GB 3985771 A GB3985771 A GB 3985771A GB 3985771 A GB3985771 A GB 3985771A GB 1311078 A GB1311078 A GB 1311078A
Authority
GB
United Kingdom
Prior art keywords
clock
signals
circuit
line
integrators
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3985771A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1311078A publication Critical patent/GB1311078A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection

Abstract

1311078 Digital data storage INTERNATIONAL BUSINESS MACHINES CORP 25 Aug 1971 [28 Sept 1970] 39857/71 Heading G4C [Also in Division H3] A circuit for regenerating data pulses D under the control of clock signals C comprises four integrators controlled respectively by +D and +C, +D and -D and +C, -D and - C, the larger output from each pair of integrators being fed to a respective input of a comparator to provide an output signal. Increased noise discrimination can be obtained since integration can be continued in each channel while the other channel is being reset. The circuit shown receives magnetically recorded data D at 12, differentiates it at 13 and feeds it to a phase splitter providing +D and - D and which may include base line and peak shift compensating arrangements. The resulting + D signal is shown at 10 (Fig. 2) and is in NRZ form. The data signals, via a circuit VFC, also provide a clock signal 21 on line 25 and a cell centre clock +C (22) on line 23 as well as a - C clock on line 24. Integrators 33, 34, 33<SP>1</SP>, 34<SP>1</SP>, under the control of respective D and C signals, integrate the current from sources 57, 58, 57<SP>1</SP>, 58<SP>1</SP> to produce the rising portion of respective waveforms 35, 36, 35<SP>1</SP>, 36<SP>1</SP>, the following portions being produced by constant current discharge. The larger of each pair of these waveforms is selected at 38 and 39 to operate a comparator 40 when the latter is enabled by clock 21 under the control of a transistor 46. The resulting output 125 is used to set a latch 51 to provide the regenerated output 126. Modification.-Base line recovery and peak shift correction is provided by adding transitions 60, 61 to the input waveform and holding the integrated level when clock 22 is positive and the data. signal negative, as shown dashed in waveform 35-41. PE or DFE signals may also be regenerated, e.g. by adding an exclusive OR circuit (Figs. 4 and 5, not shown) as well as NRZ and FFK signals.
GB3985771A 1970-09-28 1971-08-25 Digital data signal detection circuits Expired GB1311078A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US7614570A 1970-09-28 1970-09-28

Publications (1)

Publication Number Publication Date
GB1311078A true GB1311078A (en) 1973-03-21

Family

ID=22130192

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3985771A Expired GB1311078A (en) 1970-09-28 1971-08-25 Digital data signal detection circuits

Country Status (3)

Country Link
JP (2) JPS5240555B1 (en)
FR (1) FR2105862A5 (en)
GB (1) GB1311078A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2408891A1 (en) * 1977-11-14 1979-06-08 Cii Honeywell Bull ELECTRICAL SIGNAL SUITE INTEGRATION DEVICE

Also Published As

Publication number Publication date
JPS5240555B1 (en) 1977-10-13
DE2141714A1 (en) 1972-04-06
DE2141714B2 (en) 1977-01-27
FR2105862A5 (en) 1972-04-28
JPS5371883U (en) 1978-06-15
JPS5623072Y2 (en) 1981-05-29

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee