GB1308321A - Electric logic circuit arrangements - Google Patents

Abstract

1308321 Transistor logic circuits GENERAL ELECTRIC CO Ltd 24 June 1970 [21 May 1969] 25956/69 Heading H3T Two logic elements 10, 11 (block 7) are controlled by different clock trains # 1 , # 2 to be connected alternately to a common conductor 9, whereby for example they may be connected, respectively to further elements 10, 11 (block 8) also controlled by # 1 and # 2 . The blocks 7, 8 are separate integrated circuits. The elements include two F.E.T.s (1, 2, Fig. 1, not shown) in series between supply lines, their junction being connected through the source-drain path of a further F.E.T. 6 to an output terminal; the input signal controls one of the series F.E.T.'s, and the other one and the gating F.E.T. are controlled by the clock. The elements may be cross-coupled to form bi-stables, or may include extra F.E.T.'s across the input-receiving series F.E.T. to give a NOR function. To prevent spurious operation due to spikes produced in one clock period as a result of the discharging of circuit capacitance following the signal of the previous clock period, buffer stages such as 14 are included, gated by the opposite clock pulse to that of its associated element 11.