GB1299530A - Decoding circuit - Google Patents

Decoding circuit

Info

Publication number
GB1299530A
GB1299530A GB44747/70A GB4474770A GB1299530A GB 1299530 A GB1299530 A GB 1299530A GB 44747/70 A GB44747/70 A GB 44747/70A GB 4474770 A GB4474770 A GB 4474770A GB 1299530 A GB1299530 A GB 1299530A
Authority
GB
United Kingdom
Prior art keywords
transistor
capacitor
input
long
flyback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB44747/70A
Inventor
Charles Edward Owen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to GB44747/70A priority Critical patent/GB1299530A/en
Priority to BE769442A priority patent/BE769442A/en
Priority to FR7126011A priority patent/FR2106624B1/fr
Priority to IT26821/71A priority patent/IT984886B/en
Priority to AU31353/71A priority patent/AU453723B2/en
Priority to DE19712138928 priority patent/DE2138928C/en
Priority to JP46063096A priority patent/JPS5135104B1/ja
Priority to ES394755A priority patent/ES394755A1/en
Priority to CA122727A priority patent/CA921571A/en
Priority to CH1356671A priority patent/CH536047A/en
Priority to NL7112771A priority patent/NL7112771A/xx
Priority to SE11888/71A priority patent/SE365364B/xx
Publication of GB1299530A publication Critical patent/GB1299530A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902Pulse width modulation; Pulse position modulation

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

1299530 Data storage INTERNATIONAL BUSINESS MACHINES CORP 19 Sept 1970 44747/70 Heading G4C [Also in Division H3] A decoding circuit for decoding a train of input pulses, the pulses being spaced from each other by one of two nominal intervals, uses each pulse to cause flyback in a sawtooth, an output being produced whenever the sawtooth passes a threshold, the flyback having one of two different magnitudes according to the presence or absence of an output, these magnitudes being fixed so that displacement of an input pulse from its nominal position dces not effect the time at which the succeeding ramp either reaches or, but for an intervening flyback, would have reached the threshold. In Fig 1, the input 1 has a long interval between consecutive pulses to represent "1" and two-thirds this interval to represent "0" The sawtooth generator is basically a Miller integrator, with controlling capacitor 3 and Darlington pair 4, 5. Each ramp is produced by discharge of 3 via resistors 6, 7 and transistor 8. When the (negative-going) ramp goes below a threshold E, a long-tailed comparator 18, 19 sets a trigger 2 to produce an output T indicating "1" A capacitor 9 normally charges via resistors 13, 14, but each input pulse at 1 reduces the charging voltage by enabling transistor 11 to provide a shunt of resistance depending on the presence or absence of T at transistor 12. The reduction in charging voltage for capacitor 9 charges capacitor 3 (flyback). The ramp slope is varied to compensate for long-term frequency variations (due to speed variation in the drum or disc from which input 1 comes) by using the level on a capacitor 21 via a low-pass filter 22 to control the resistance of the discharge path 6, 7, 8 of ramp capacitor 3, at transistor 8. While the sawtcoth is above a reference level defined by a potentiometer 23, as determined by a long-tailed comparator 24, 25, capacitor 21 is charged via a transistor 26 (except that in the case of a preceding "0" bit, half the current is diverted via a transistor 27 due to the control of a transistor 29 by trigger 2, to provide for the fact that the sawtcoth is below the reference level for twice as long for a "1" as for a "0"). While the sawtooth is below this reference level, capacitor 21 discharges via transistor 27, so that in the absence of frequency variations, the average level on capacitor 21 is zero. Non- ideal flyback can be compensated for by a capacitor (short time constant) connected between transistor 11 collector and transistor 24 base. Synchronization of the circuit is achieved by an initial block of zerces followed by a block of ones. The invention can be applied to double-frequency encoded input (having regular clock pulses, a data pulse being present or absent half way between consecutive clock pulses for "1" and "0" respectively, viz. long interval for "0", two short intervals for "1") by subtracting the long interval indicating signal from the input signal and dividing the remainder by two to get pulses indicating "1"s. Decoding of address marks represented by omission of the clock pulses can also be done using suitable logic.
GB44747/70A 1970-09-19 1970-09-19 Decoding circuit Expired GB1299530A (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
GB44747/70A GB1299530A (en) 1970-09-19 1970-09-19 Decoding circuit
BE769442A BE769442A (en) 1970-09-19 1971-07-02 DIGITAL DATA DECODING DEVICE
FR7126011A FR2106624B1 (en) 1970-09-19 1971-07-06
IT26821/71A IT984886B (en) 1970-09-19 1971-07-09 DECODING CIRCUIT
AU31353/71A AU453723B2 (en) 1970-09-19 1971-07-19 Decoding circuit
DE19712138928 DE2138928C (en) 1970-09-19 1971-08-04 Decoder for interval-coded pulse trains
JP46063096A JPS5135104B1 (en) 1970-09-19 1971-08-20
ES394755A ES394755A1 (en) 1970-09-19 1971-09-02 Decoding circuit
CA122727A CA921571A (en) 1970-09-19 1971-09-14 Decoding circuit
CH1356671A CH536047A (en) 1970-09-19 1971-09-16 Decoder for interval-coded pulse trains
NL7112771A NL7112771A (en) 1970-09-19 1971-09-17
SE11888/71A SE365364B (en) 1970-09-19 1971-09-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB44747/70A GB1299530A (en) 1970-09-19 1970-09-19 Decoding circuit

Publications (1)

Publication Number Publication Date
GB1299530A true GB1299530A (en) 1972-12-13

Family

ID=10434583

Family Applications (1)

Application Number Title Priority Date Filing Date
GB44747/70A Expired GB1299530A (en) 1970-09-19 1970-09-19 Decoding circuit

Country Status (10)

Country Link
JP (1) JPS5135104B1 (en)
BE (1) BE769442A (en)
CA (1) CA921571A (en)
CH (1) CH536047A (en)
ES (1) ES394755A1 (en)
FR (1) FR2106624B1 (en)
GB (1) GB1299530A (en)
IT (1) IT984886B (en)
NL (1) NL7112771A (en)
SE (1) SE365364B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE790871A (en) * 1971-11-12 1973-05-03 Shell Int Research METHOD OF SEPARATION OF LIQUIDS AND SOLIDS BY MEANS OF FILTRATION
JPS5128610A (en) * 1974-09-04 1976-03-11 Hitachi Ltd Museiryushimoota no sokudoseigyokairo
JPS5852438B2 (en) * 1976-01-29 1983-11-22 株式会社東芝 Control device for commutatorless motor
JPS60124153U (en) * 1984-01-31 1985-08-21 パイオニア株式会社 Data signal reading device
US5400022A (en) * 1993-10-15 1995-03-21 Apple Computer, Inc. Pulse code bit cell demodulation
FR3124157B1 (en) 2021-06-22 2023-05-05 Psa Automobiles Sa motor vehicle interior lining element

Also Published As

Publication number Publication date
JPS4716912A (en) 1972-04-15
DE2138928A1 (en) 1972-03-23
FR2106624A1 (en) 1972-05-05
AU3135371A (en) 1973-01-25
JPS5135104B1 (en) 1976-09-30
BE769442A (en) 1971-11-16
IT984886B (en) 1974-11-20
CH536047A (en) 1973-04-15
FR2106624B1 (en) 1974-04-26
SE365364B (en) 1974-03-18
DE2138928B2 (en) 1972-11-30
ES394755A1 (en) 1975-08-16
NL7112771A (en) 1972-03-21
CA921571A (en) 1973-02-20

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee