GB1292973A - Multi-valued logic circuits - Google Patents

Abstract

1292973 Logic circuits A R TURQUETTE 14 Nov 1969 55922/69 Heading G4H A logic circuit comprises M input circuits P 1 , P 2 , P 3 , each having M output terminals, each input circuit energizing predetermined ones of the output terminals with signals representative of a logic state assumed by the input circuits, M output signal receivers 1, M- 1 binary gating devices 2, each of the gating devices connecting a first receiver of lower numerical order with a second receiver of the next higher numerical order when in one state and disconnecting the first and second receivers when in the other binary state, M connecting means, one of the connecting means coupling the first output terminals of lowest numerical order of all of the input circuits to the first of the receivers and each subsequent connecting means coupling the next numerical order output terminals of all of the input circuits to actuate a respective gating device of successively decreasing numerical order starting with that of higher numerical order, whereby when the ith output terminal of any one of the input circuits is energized, M - i + 1 receivers are energized. Fig. 21 shows a "NAND" circuit with M=3 wherein the receivers are lamps and the gating devices are relays, the contacts of which are closed when the relay coil, represented by a circle, is deenergized. This logic circuit, as well as other logic circuits, is derived from theorems of M- valued logic which are proved in the description.