GB1277305A - Method of and circuit arrangement for reducing the dissipation caused by the information currents in a core store - Google Patents

Abstract

1277305 Magnetic storage arrangements LICENTIA PATENT - VERWALTUNGS GmbH 17 Sept 1969 [17 Sept 1968] 45874/69 Heading H3B [Also in Division G4] Power dissipation in a known coincident current n bit word store is reduced by storing any word having at least n/2 "0" bits in an inverted form, a record of inversion being made in an n+ 1th bit. The known store comprises n planes, Fig. 2, one bit of each word being stored per plane, and each plane has an inhibit wire J. The nth plane contains check bits each of which is written as either "0" or "1" to make the number of "1" bits of a respective word, together with its check bit, even. Each word thus comprises n - 1 information bi s and a check bit. Power dissipation in this known store is greater when a "0" is written in a bit than when a "1" is written, because of the use of the inhibit wire, and inversion of information thus may allow lower operating temperatures. According to the invention, the number of "0" bits in the word may be ascertained, Fig. 3, by connecting the inhibit signals JA from the information register to one input of a differential amplifier 31 via equal resistors (not shown) which form a D/A converter 30, the second input of amplifier 31 being from a reference potential U ref chosen so that the amplifier gives a "1" output for n/2 or more "0" inhibit inputs. This output is stored in an n + 1th plane, and is also gated with the inhibit signals JA, Fig. 4 (not shown), to produce inhibit drives KJA for the planes, inverted as required. The signals stored in the n + 1th plane are used to reinvert the information of the word on readout.