GB1266029A - - Google Patents

Info

Publication number
GB1266029A
GB1266029A GB1266029DA GB1266029A GB 1266029 A GB1266029 A GB 1266029A GB 1266029D A GB1266029D A GB 1266029DA GB 1266029 A GB1266029 A GB 1266029A
Authority
GB
United Kingdom
Prior art keywords
register
address
blocking
bits
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1266029A publication Critical patent/GB1266029A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
GB1266029D 1968-09-03 1969-05-20 Expired GB1266029A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US75700268A 1968-09-03 1968-09-03

Publications (1)

Publication Number Publication Date
GB1266029A true GB1266029A (en:Method) 1972-03-08

Family

ID=25045953

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1266029D Expired GB1266029A (en:Method) 1968-09-03 1969-05-20

Country Status (2)

Country Link
US (1) US3665175A (en:Method)
GB (1) GB1266029A (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2181849A1 (en:Method) * 1972-04-24 1973-12-07 Ibm

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4227244A (en) * 1978-11-30 1980-10-07 Sperry Corporation Closed loop address
JPS62237522A (ja) * 1986-04-08 1987-10-17 Nec Corp 情報処理装置
US5070502A (en) * 1989-06-23 1991-12-03 Digital Equipment Corporation Defect tolerant set associative cache
US6741257B1 (en) 2003-01-20 2004-05-25 Neomagic Corp. Graphics engine command FIFO for programming multiple registers using a mapping index with register offsets

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2181849A1 (en:Method) * 1972-04-24 1973-12-07 Ibm

Also Published As

Publication number Publication date
US3665175A (en) 1972-05-23

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee