GB1265798A - - Google Patents

Info

Publication number
GB1265798A
GB1265798A GB1265798DA GB1265798A GB 1265798 A GB1265798 A GB 1265798A GB 1265798D A GB1265798D A GB 1265798DA GB 1265798 A GB1265798 A GB 1265798A
Authority
GB
United Kingdom
Prior art keywords
carry
signal
propagate
paths
mosts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1265798A publication Critical patent/GB1265798A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
GB1265798D 1968-08-13 1968-08-13 Expired GB1265798A (enrdf_load_stackoverflow)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3869968 1968-08-13

Publications (1)

Publication Number Publication Date
GB1265798A true GB1265798A (enrdf_load_stackoverflow) 1972-03-08

Family

ID=10405148

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1265798D Expired GB1265798A (enrdf_load_stackoverflow) 1968-08-13 1968-08-13

Country Status (1)

Country Link
GB (1) GB1265798A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0097779A1 (en) * 1982-06-28 1984-01-11 International Business Machines Corporation Logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0097779A1 (en) * 1982-06-28 1984-01-11 International Business Machines Corporation Logic circuit

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees