GB1264824A - - Google Patents

Abstract

1,264,824. Transistor bi-stable circuits. GENERAL INSTRUMENT MICRO-ELECTRONICS Ltd. 17 June, 1969, No. 30707/69. Heading H3T. [Also in Divisions G4-G6] Accelerated carry up or down is effected by storing a pre-carry condition in the capacitance of an FET between count signals so that the succeeding count signal renders another FET conductive to produce carry virtually simultaneous with the count signal. NOR gate G1 or G2 controlled by inverse signals from a decimal counter which may be B.C.D. produce an output 1 so that G3 produces 0 and AND gate G4 produces 0 when (a) the counter is at 9 and going up or at 0 and going down; and (b) in the interval between count signals. In these conditions a pre-carry signal is stored in the capacitance of an FET (Q3, Fig. 2) in G4. When the invert of the count signal changes from 1 to 0 an FET (Q1, Fig. 2) in NOR gate G5 conducts so that a push-pull gate G7 produces a carry output. Feedback from inverter G6 combined with count signal in AND gate G8 provides stability. Circuit details.-The FET system of Fig. 2 acts as a bi-stable circuit with the arrangement to the right of point B held quiescent by feedback from point 16 through Q7 to 18 as long as no pre-carry signal appears at point A. When this happens the potential on the gate of Q3 from count stores a charge on its capacitance and the succeeding loss of potential from count on the gate of Q2 upsets the bi-stable so that Q1, Q2, Q8 conduct to act in push-pull on Q5, Q6 to produce an output.