GB1254820A - Improvements relating to information transmission systems - Google Patents

Improvements relating to information transmission systems

Info

Publication number
GB1254820A
GB1254820A GB3249070A GB3249070A GB1254820A GB 1254820 A GB1254820 A GB 1254820A GB 3249070 A GB3249070 A GB 3249070A GB 3249070 A GB3249070 A GB 3249070A GB 1254820 A GB1254820 A GB 1254820A
Authority
GB
United Kingdom
Prior art keywords
count
counter
input
gate
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3249070A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Priority to GB3249070A priority Critical patent/GB1254820A/en
Publication of GB1254820A publication Critical patent/GB1254820A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/02Delta modulation, i.e. one-bit differential modulation

Abstract

1,254,820. Delta encoder. TEXAS INSTRUMENTS Ltd., and C. S. DENBRINKER. 3 July, 1970, No. 32490/70. Heading G4H. In a delta encoder (Fig. 1) in which the counter 3 in the transmitter is incremented or decremented one unit in accordance with whether an input at terminal 1 exceeds or is less than the previous input level represented by the count in counter 3 a count up/count down pulse being transmitted via a gate 7 through the receiver RX, when the counter is full or empty, gate 7 is inhibited and count up or count down pulses respectively are transmitted so that the receiver counter is stepped to bring it into synchronism with the transmitter counter. The counters ignore pulses tending to make them exceed their maximum and minimum values so that if the input is above the level represented by the counter 3 the counter will remain full at this time. If however the maximum count represents the maximum possible value of the input when the input is at its maximum the comparator 2 will result in alternate count up and count down signals being generated but the count down signals will not be transmitted since gate 7 is inhibited during them. As described the input signal is in analogue form the count in counter 3 being converted to analogue form in a D/A converter 4, gates 12, 13 connected to the outputs of counter 3 control the closing of gate 7 and the transmission of the pulses at full count and empty count. At the receiver a counter 15 accumulates the transmitted pulses, the counter outputs being connected to digital to analogue converter 16. Alternatively the input or output could be digital. The system may be modified to transmit three state signals representing count up, count down and no change instead of the two state signals of the embodiment of Fig. 1.
GB3249070A 1970-07-03 1970-07-03 Improvements relating to information transmission systems Expired GB1254820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB3249070A GB1254820A (en) 1970-07-03 1970-07-03 Improvements relating to information transmission systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3249070A GB1254820A (en) 1970-07-03 1970-07-03 Improvements relating to information transmission systems

Publications (1)

Publication Number Publication Date
GB1254820A true GB1254820A (en) 1971-11-24

Family

ID=10339393

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3249070A Expired GB1254820A (en) 1970-07-03 1970-07-03 Improvements relating to information transmission systems

Country Status (1)

Country Link
GB (1) GB1254820A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2570831A1 (en) * 1984-09-21 1986-03-28 Efcis ANALOG SIGNAL LEVEL DETECTOR

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2570831A1 (en) * 1984-09-21 1986-03-28 Efcis ANALOG SIGNAL LEVEL DETECTOR
EP0178209A1 (en) * 1984-09-21 1986-04-16 STMicroelectronics S.A. Analogous signal level detector
US4721865A (en) * 1984-09-21 1988-01-26 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux - Efcis Analog signal level detector

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