GB1239922A - Modulated pulse computing circuits - Google Patents

Abstract

1,239,922. Pulse width computation. K.D.G. INSTRUMENTS Ltd. 26 July, 1968 [27 April, 1967], No. 19529/67. Heading G4G. A pulse width modulator (Fig. 4) comprises an integrator with a D.C. amplifier and capacitance feedback C excited by input signal V 1 over resistance R; the integrator output operating a Schmitt trigger whose trip levels are O and V 2 which gates a voltage-V 3 to amplifier input over further resistance R for removal at level V 2 and application at level O. For zero input the integrator output oscillates with equal rise and fall times t 1 = t 2 CRV 2 /V 3 , and for V 1 input t 1 = CRV 2 /V 3 -V 1 t 2 = CR V 2 /V 1 so that mark space ratio = t 1 /t 2 = V 1 /V 3 -V 1 and V 1 /V 3 = t 2 /t 1 +t 2 (Fig. 5, not t 2 V 3 -V 1 V 3 t 1 +t 2 shown), and if the trigger switches an output gate (not shown) between limits of V and +V 4 , mean value of output the gate level voltages V 3 , V 4 being controllably variable. The trigger may derive a P.W.M. output signal indirectly by utilizing gate switching voltage V 4 in synchronism with trigger operation (Fig. 6A, not shown); the output being rectified, smoothed, and D.C. amplified. If V 3 = a V cc , V 4 = b V cc where V cc is a conb stant voltage, V 0 = - V 1 - so that the device a functions as amplifier (Fig. 6B, not shown) applicable to split field servomotors or pulse width modulated audio amplification. Switching may be by thyristor. For multiplication, the switched output voltage V 4 is derived from input V 1 over buffer D, the switched feedback voltage V 3 from a reference source, and the voltage V 1 from input X, while the P.W.M. A feeds rectifier-filter B and output amplifier C to produce output voltage V 0 = X Y/V 3 (Fig. 6C). For division, voltages V 3 and V 4 are transposed (Fig. 6D, not shown), so that V 0 = V 4 X/Y, and for reciprocation (Fig. 6E, not shown), voltage V 1 is taken from a reference source so that V 0 = V 1 V 4 1/Y. Y For multiplication and division, voltages V 1 , V 3 and V 4 are derived from inputs X, Z and Y so that V 0 = XY/Z (Fig. 6F, not shown), and for squaring, voltage V 3 is taken from a reference source, V 1 from input X, and V 4 from input X over buffer amplifier D (Fig. 6G) so that V 0 =X 2 /V 3 . Similarly for square rooting (Fig. 6I, not shown), voltage V 3 is derived from output V 0 over a buffer amplifier, V 4 from input Y over a buffer amplifier, V 1 from input X so that V 0 = #XY, and if V 4 is derived from a reference voltage V 0 = k#x (Fig. 6H, not shown). Power and root circuits may be cascaded for derivation of higher powers and roots. Fig. 7 shows a circuit for introducing the transfer function into a P.I.D. control system, wherein (Fig. 9) input voltage V 1 is applied over resistance R to an amplifier/capacitance feedback integrator and Schmitt trigger operating as a P.W.M. which drives gates 1, 2 modulating voltages V 4 fed through rectifier and filter to develop output voltage V 0 , and V 3 fed back over series resistance Rd and shunt capacitance Cd and over a buffer amplifier PQ and capacitance C 1 in series with resistance R to the integrator input. A mathematical analysis is given. The P.W.M. may be applied to digital voltage measurement by making the output mark/space ratio proportional to input voltage i.e. where V 3 is reference voltage and modulating the t 2 pulse with clock pulse at a multiplier of pulse frequency so that the PRF pulses are similarly modulated; the latter being used by decade division to time the t 2 pulse counter (Fig. 8, not shown). Integral transistorized buffer amplifiers having negative feedback are provided for applying the X, Y, Z signals to the computing circuitry (Fig. 10, not shown); similar integrated circuits comprising integrating operational amplifiers with negative capacitance feedback followed by Schmitt trigger and switching transistor; the input to the integrating circuit . being derived from a transistorized differential amplifier receiving the X and Z voltages, the switching transistor opening to apply (X-Z) to the integrating circuit, and closing to apply X thereto so that the output is pulsed of mark/space ratio dependent on X and Z (Fig. 11, not shown). The output pulses are applied to transistor gate a Y voltage, the resultant pulses being capacitance smoothed, amplified, and applied to an output terminal to represent XY/Z; the signal being also applied over transistor circuitry to current or voltage metering outputs. Detailed component values are given.