GB1237451A - Improvements in or relating to circuit arrangements for digital integration - Google Patents

Abstract

1,237,451. Digital electric integrator. PLESSEY CO. Ltd. 8 Aug., 1969 [10 May, 1968], No. 22370/68. Heading G4A. Circuit for iteratively integrating a first function with respect to a second function has a multiplier multiplying the functions together and an adder receiving the multiplicand and the previous integrated step, the result being the integrated output. The Specification describes circuits carrying out integrations according to one of the approximations where I = #Y.#X A circuit carrying out the integration according to equation (c) is described with respect to Fig. 5. Binary data #x/2 is fed to a shift register R1 by clock signals # under the control of signal A. Similarly binary data Y is fed to register R2. The least significant bit of #x/2 sets flip-flop B1 to allow Y to be fed through adder A1 to be stored in register R4 if the bit is " 1". Data is recirculated through the registers under control of the clock pulses, the Y data passing stage R3 to be shifted one place to the left so that on multiplication by the next most significant bit of #x the partial product is correctly added to the previous partial product. The result is fed to a further multiplier 10 and a register 9 to an adder 11 and to register 12. If the output of register R4 is #x/2.Yn 1 then multiplier 10 which contains a 1 bit shift register R4 effectively multiplying by 2 will supply #x/2(3Yn-1) when register 9 which delays by one word and inverts will supply Yn- 2 therefore adder A4 will supply register 12 with In - 1 + #x/2(3Yn -1 - Yn - 2) which is the required value. The integrator may be constructed in integrated circuitry with an output from the multiplier being provided so that the circuit can multiply and integrate.