GB1220505A - Timing pulse generator - Google Patents

Abstract

1,220,505. Transistor pulse circuits. INTERNATIONAL BUSINESS MACHINES CORP. 6 June, 1968 [14 June, 1967], No. 26879/68. Heading H3T. In a pulse generator having input pulses applied to a gate 4 via a delay device 3 and to the set input of a latch or bi-stable circuit 2, the output from the latch circuit is connected to the gate 4, so as to enable the gate to pass signals from the delay device 3, and is also connected to a control circuit including a single-shot multivibrator 6 and/or 7 which is effective when activated to reset the latch and to hold the latch reset for a time at least equal to the period of the multivibrator. As shown input signals (A, Fig. 3, not shown) at E trigger tunnel diode TD1 to produce negative pulses (B) which are inverted and differentiated in circuit 10 which includes a coaxial inverter I.C. to produce positive pulses (C) at the input to the latch or bi-stable circuit 2. This causes the bi-stable circuit 2 to attain the set state in which tunnel diodes TD2 and TD4 are in their high voltage state, diodes D1 and D3 are OFF and transistor Tl is ON. The tunnel diode TD3 of the gate 4 is biased near its peak current and when the delayed signal (G) from delay line 3 occurs it is triggered to produce a negative pulse (R) at the output S which controls a scanning device (5, Fig. 1, not shown), of an oscilloscope. The output (E) of the transistor T1 is passed via a coil H, which introduces a time lag, to the input of a single shot circuit 6 which turns OFF transistor T3. The output (k) of T3 is fed via a delay line 8 and via a further single shot circuit 7 to an OR gate 9. The delayed output (M) from line 8 activates gate 9 causing T6 to conduct and produce a negative output (N) which resets the bistable circuit 2. The tunnel diodes TD2, TD3 and TD4 assume their low voltage state, transistor T1 turns OFF and a positive output pulse (R) is produced. At the end of the unstable period of the single shot circuit 6 the transistor T5 is turned OFF so that the single shot circuit 7 obtains its unstable state. The output (L) of this circuit causes T7 to conduct so that the bi-stable circuit 2 is held in the reset state until the end of the unstable period of circuit 7 when it can be triggered into the set state by the next input pulse.