GB1217672A - Improvements in or relating to telecommunications systems - Google Patents

Improvements in or relating to telecommunications systems

Info

Publication number
GB1217672A
GB1217672A GB5387966A GB5387966A GB1217672A GB 1217672 A GB1217672 A GB 1217672A GB 5387966 A GB5387966 A GB 5387966A GB 5387966 A GB5387966 A GB 5387966A GB 1217672 A GB1217672 A GB 1217672A
Authority
GB
United Kingdom
Prior art keywords
oscillator
derived
frequency
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5387966A
Inventor
Donald Francis Bowman
Allen Allister Claxton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co PLC
Original Assignee
General Electric Co PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co PLC filed Critical General Electric Co PLC
Priority to GB5387966A priority Critical patent/GB1217672A/en
Publication of GB1217672A publication Critical patent/GB1217672A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0676Mutual
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

1,217,672. Multiplex pulse code signalling. GENERAL ELECTRIC, and ENGLISH ELECTRIC COMPANIES Ltd. 2 Feb., 1968 [1 Dec., 1966], No. 53879/66. Heading H4L. In a P.C.M. communication system for twoway signalling, each station has a local oscillator which controls the repetition frequency of the transmitted pulse signal and a phase-locking control system for the oscillator which operates in dependence upon a comparison of a signal derived from the received pulse signal with a signal derived from the oscillator the two signals having nominally the same frequency which is a submultiple of the frequency of the oscillator. Fig. 1 shows a system, not incorporating the invention, in which two exchanges 1, 2 are linked 3, 4 for two-way P.C.M. speech signals, the transit times of the paths 3 and 4 being shown as delays 13, 14. Each exchange has a bit-frequency oscillator 5 from which timing signals for coding, decoding, multiplexing and demultiplexing are derived at 6. The incoming bit frequency is derived at 11 and compared with the output of oscillator 5 in a phase comparator 12 whose -output controls the frequency of oscillator 5. The invention provides a modification, Fig. 2, in which the comparison at 12 is made at the frame rate derived at 19 from the incoming signal and the frame rate also is derived at 21 from the incoming signal and supplied to a further phase comparator 20 where it is compared with the output of oscillator 5 divided at 17 to the frame rate. The output of the comparator 20 adjusts a variable delay line 18 which alternatively may be placed in the outgoing line. In a further modification Fig. 3 (not shown) the incoming signals are supplied to a buffer store from which they are read subsequently, and variable delay line is replaced by a monstable circuit which is voltage-controlled to vary the duration of its output pulses to provide a variable time delay.
GB5387966A 1966-12-01 1966-12-01 Improvements in or relating to telecommunications systems Expired GB1217672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB5387966A GB1217672A (en) 1966-12-01 1966-12-01 Improvements in or relating to telecommunications systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5387966A GB1217672A (en) 1966-12-01 1966-12-01 Improvements in or relating to telecommunications systems

Publications (1)

Publication Number Publication Date
GB1217672A true GB1217672A (en) 1970-12-31

Family

ID=10469284

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5387966A Expired GB1217672A (en) 1966-12-01 1966-12-01 Improvements in or relating to telecommunications systems

Country Status (1)

Country Link
GB (1) GB1217672A (en)

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