GB1211493A - Improvements in or relating to signal-processing systems - Google Patents

Abstract

1,211,493. Automatic exchange systems. SIEMENS A.G. 4 Feb., 1969 [6 Feb., 1968], No. 5921/69. Heading H4K. A processor conditions peripheral units to exhibit priority in making demands on processor time when the function of the units requires quick response. The various circumstances in which a processor attributes priorities are described in the context of the exchange network illustrated in Fig. 1. A main exchange network KF serves subscribers Tnsi having impulse transmitting dials and subscribers Ttast having key sending sets. Digits are received by an allocated one of circuits W11 to W1n, and if such a circuit is connected to a key sending-set subscriber the processor ZE over its distributer/ connector Id conditions the circuit to call on the services of the processor as a matter of priority as key-sent digits are received quicker than normal processing would collect. The main exchange also serves a satellite switching centre kf over lines t11 to t1e, ringing current to a satellite station being disconnected at the main exchange in response to reply at the satellite. Since the reply signal is delayed somewhat by transmission from the remote satellite the relay sets R11 to R1l serving the satellite exchange lines are set up to exhibit priority at the ringing stage to obtain rapid processing of the reply signal so as to disconnect ringing before it becomes coupled to the receiver of the called satellite subscriber. The exchange also serves private branch exchanges N1 and N2 which provide for automatic dialling through to extensions over exchange lines such as D1, D2. Circuits such as W21 to W2o are employed for repeating dialled digits to other exchanges, including a PBX, and when such a circuit is employed with repeating PBX extension digits the processor sets the circuit up to exhibit priority for the handling of an "end-of-dialling" signal from the PBX. A fast response is necessary in this context because a PBX will subsequently revert acknowledgment and clearing signals that would be simulated by the dialling signals were the pertinent receiver in the impulse repeating circuit not blocked. When an "endof-dialling" signal is received at the repeating circuit it calls in the processor to unblock the receiver as a matter of priority. The priority indication for a peripheral unit, such as the exchange circuits indicated above, may be established in some circumstances by the unit itself. The processor ZE may serve a number of groups of peripheral units, such as those based on the main exchange KF, each group having its own distributer/connector Id and a buffer store as an interface to the processor. The system may employ three levels of priority.