1,196,829. Data processor terminal apparatus. ING. C. OLIVETTI & C. S.p.A. 20 Sept., 1968 [3 Oct., 1967], No. 44895/68. Heading G4A. A terminal apparatus adapted to transmit data to and receive data from a central data processor unit comprises a keyboard or other imprint device for supplying imprint data, a store, a display screen and a control arrangement wherein the control arrangement causes the exchange of a block of information between the apparatus and the central unit to take place by way of a predetermined dialogue procedure between the apparatus and the central unit, and causes the block of information to be entered in the store before it is displayed on the screen. A terminal unit connected to a central computer has a keyboard, a recirculating magneto-strictive store and a cathode-ray tube display. Blocks of data from a central processor each block prefixed by a start of block character and followed by an end of block or an end of message character, are transmitted via a line controller 4 which performs a preliminary dialogue between the terminal and processor to establish a channel of communication. The delay line holds one block of characters, each character containing 10 bit periods holding a seven bit character, a parity bit and two marker of service bits. The delay line also holds a start timing bit C5 and a parity bit PCS occurring before the block of characters. The start timing bit C5 on being read out triggers a timer 23 causing production of 256 trains of ten signals D1-D10 on separate lines identifying the bit period of each character. Entry of data from the keyboard.-The keyboard has a storage reservation key allowing the store to be reserved for entry of characters from the keyboard which, if a signal ASTAL from the line controller is present assigning the store to the keyboard causes entry of the signal C5 into stage R1 of the shift register 22 and also a service bit bs in the first stage R1 in the following bit period D1. A circuit 26 produces a simple parity bit which is entered in the last stage of the register during bit period D10. The bits introduced circulate during the store reservation phase until a character is posted on the keyboard. This generates a signal ICTA causing the read out service bit bs to be reinserted shifted by one digit period. Read out of the bit also produces a signal CAR causing entry of the character from the keyboard into register 22. The following characters are entered in a similar manner. Character display.-In the phases where the store is free (signal L) or assigned to the keyboard (AST) provided the reading command LG is not present, the characters circulating in the delay are displayed on the screen. Under these conditions a signal ASTAL from circuit 76 at each bit period D1 transfers the characters from register 22 to register 51 to be decoded by decoder 54 having a number of output wires equal to the number of different characters allowed, each wire threading predetermined cores in a 7 x 5 matrix 55 such that when a wire is activated the cores set spatially form the character required. A counter 56 advanced by the timing signal C5 initially activates the first row of the matrix causing read out of the first row of all the characters in a cycle to a register 59 and thence to a cathode-ray tube. The tube screen is divided into eight bands each having seven lines each band containing 32 digits and the lines are scanned in the order the top line of each row, the second line of each row &c. in synchronism with the cycling of the contents of the delay line so that each character stored is built up in the display. The display also has means for displaying the bit bs in the storage cell following the last character entered, the display appearing as a horizontal dash due to five 1 bits being entered into register 59 via gate 80 during the activation of the seventh row of the matrix if bs = 1. Displacement of the service bit bs from one cell to another can occur under the control of the keyboard which has a forward spacing key causing regeneration of bit bs to the next following cell, and a back spacing and cancellation key which, when the service bit is read on line 72 generates the bit on line 73 and not on line 21. A row jump key is provided causing the next character to be entered at the beginning of the next row. The key generates a signal BSs preventing regeneration of signal bs until counter 61 produces signal FIRI at the commencement of the next row. A tabulating key is also provided allowing the digits in each row to be tabulated on the least significant digit, the most significant digit being entered in the last position in a row and then shifted as the next digit is entered in the row vacant last position. Operation of the key prevents regeneration of the service bit until the signal FIR1 occurs whereon the service bit is entered in the last position of the row and a dummy bit bl is entered in position D2 of the cell the data can then be read in and the bit bs shifted. On readout bit bl and the character are shifted by one cell allowing the next digit to be entered in the cell containing bit bs. On the next readout all the characters between the bits bl and bs are shifted thus allowing data to be entered with the least significant digit always held in the end cell of a row.