GB1192892A - Automatic Phase Correction of Digital Signals - Google Patents

Abstract

1,192,892. Multipled pulse code signalling; automatic phase control. RAYTHEON CO. 24 Sept., 1968 [2 Oct., 1967], No. 45338/68. Headings H3A and H4L. An automatic phase correction circuit for interleaving digital data trains having the same bit rate, one train having an arbitrary phase relationship and the other train having a fixed phase relationship with a clock signal, comprises means for sampling said one data train with a narrow pulse at the bit rate as derived from the clock signal, means for storing the sampled data, control means for determining when the sampling pulse coincides with a data transition of said one train and for shifting the sampling pulse away from such a transition and means for interleaving the other data train and said one data train as recovered from the storing means. In an alternative arrangement both digital data trains have an arbitrary phase relationship with the clock signal and are each treated in the manner specified above before interleaving. Circuit details.-The data signal having an arbitrary phase relationship with the clock signal is designated DATA 2 and that having a fixed phase relationship is DATA 1. Bit rate signals D, a clock signal A comprising pulses at four times the bit rate, and data transitions X of the signal DATA 2 are supplied to a NAND gate 12. The output Y of gate 12 is applied to a bi-stable device 20 having feedback 22, 24 so that its condition is inverted on reception of a pulse Y, bi-stable 20 supplying an output 1 or 0 to NAND gates 28, 32 respectively. A signal B at twice the bit rate is supplied to NAND gate 28 and this signal inverted, B, is supplied to NAND gate 32. Gates 28, 32 supply an AND gate 38 whose output C = B or B (according to the state of bi-stable 20) is supplied to a NAND gate 42 and is also fed back to the gate 12. Pulses A and D and the signal DATA 2 are supplied to a gate 42 whose output G consisting of sampled data is supplied to a bi-stable 50 acting as a store. The bi-stable 50 is reset by bit rate pulses D and supplies a signal to a NAND gate 58 also controlled by pulses D. The other signal DATA 1 is fed in inverted form to a NAND gate 62 controlled by pulses D and the outputs of gates 58, 62 are combined in interleaved form at 68. Operation.-If the resultant narrow pulse E (A.C.D) sampling DATA 2 in gate 42 coincides with a data transition as represented by signal X, this is detected by NAND gate 12 which reverses the condition of bi-stable 20 to activate a different one of the NAND gates 28, 32 so that the output C= twice the bit rate square waves B or B, is inverted. This shifts the sampling point a quarter period of the bit rate away from the transition X of DATA 2.