GB1192290A - An Echo Filtering Arrangement for Radar Systems - Google Patents

Abstract

1,192,290. Radar. THOMSON C.S.F. 19 Dec., 1968 [20 Dec., 1967; 10 May, 1968], No. 60520/68. Heading H4D. Specification describes a pulsed Doppler radar, Fig. 1, wherein, to simulate the function of an "ideal" Doppler filter, a plurality of consecutive returns, each containing echoes from the same target, are each weighted (at X) by an amount dependant on the order of the particular return within the plurality and said weighted returns are summed and wherein to overcome the necessity of storing each weighted return prior to the summation, each weighted return is consecutively fed to a summing junction # having at its other input the output of a memory device M, the output of said junction updating the memory content and providing the signal at said other input for the subsequent return. If the response of the ideal filter is H (t) and the echo signal is E(t), then the output of the filter is given by This function is approximated by the inventors as the sum over n returns of The term H(#/2 + iT), calculable by a given formula, gives the weighting factor for the particular return. In the radar of Fig. 2, step scan control B causes the antenna A n to stay in one position for such a time that n returns from the target occur. A clock Fr gates the output of coherent transmitter E at the repetition frequency; under the control of sync. circuit Sy. The received echoes are processed in receiver R and the if signals are fed to weighting amplifier. The weighting by function H(t) is performed in two stages-an analogue stage is amplifier A and a digital stage is shift circuit T 3 . The amplification of stage A is varied from one return to the next according to the stored signal in memory M, read out by the clock Fr. Negative values of this weighting are allowed for by inverter I. The partially weighted returns are fed to m Doppler channels each detecting echoes having Doppler shifts with predetermined ranges. Each channel is comprised by two sub-channels, one a "sine" channel and the other a "cosine" channel. The channels feed into and receive the content of (in the describd manner of summing junction #), memory M. Each return is time quantized at E 3 in N range gates. Memory M thus comprises 2m N storage positions. Each channel comprises a "sine" phase detector D 3 and a "cosine" phase detector respectively fed with the outputs of a local oscillation in phase quadrature. The frequency of the oscillator O, Fig. 2a (not shown), is Fm + fdi, where F m is the if frequency and fdi is a frequency different for each channel and determining the Doppler frequency range of the channel. The output of the detector D 3 is time quantized and converted to digital form in means E 3 and the digital return subjected to the second stage of weighting in shifting circuit, wherein the digital contents are shifted (i.e. multiplied) by amounts stored in memory M 2 , read out by clock Fr. The totally shifted returns are applied as explained above to summing function # 3 . The total contents of memory M are read out to utalization devised at the end of the n returns. An embodiment utalizing transmitted pulse pairs, to overcome Doppler ambiguities is also described, Fig. 8 (not shown).