GB1191843A - Improvements in or relating to Data Transmission Apparatus - Google Patents

Abstract

1,191,843. Digital transmission systems. PLESSEY CO. Ltd. 7 July, 1967 [7 July, 1966], No. 30664/66. Heading H4P. A demodulator for differential phase-shift signals comprises a unit including a delay line to which the received signal is fed, the output of the delay line being selectively fed back to its input to derive a signal delayed by a multiple of the delay line period. Transmitter.-Input binary data is converted to dibit form, the dibits controlling the phase of a two-stage counter, fed by squarewave carrier frequency clock pulses, by subtracting from the count the binary number represented by a dibit. The output from the second stage is a signal in which each dibit is represented by *1¢ cycles of a square-wave which has a phase, relative to the preceding 1¢cycles, indicative of the dibit. This signal is filtered and transmitted. Receiver.-The signal is filtered and limited, the limiter output passing to a comparator and also to a unit which samples the signal several times per cycle. The samples pass to a gated feed-back delay unit which has a basic delay of one-quarter of a carrier cycle. By repeated feed-back the samples are delayed by multiples of a quarter cycle, the delay providing three outputs equal to the limited input signal delayed by 1“, and¢ 1¥ carrier cycles. These signals pass to a comparator wherein each is compared with the limited (and undelayed) signal. The resulting three outputs are fed to respective units, each comprising a Miller integrator and a threshold unit, to develop respective outputs corresponding to the three dibit signals other than 00, these outputs passing to a circuit giving a serial output identical to the signal at the transmitter input. The sampling pulses are also passed to counter/divider which outputs a clock signal synchronized with the received data. The comparator provides a fourth output by comparison of the 1“ and 1¥ cycle delayed signals, the result passing to a fourth integrator and threshold unit. The threshold unit pulses at each dibit level transition, and at each such pulse a pulse is either inserted or removed from the sampling pulse train fed to the divider to control the phase of the counter output.