GB1191560A - Input/Output Control for a Digital Computing System. - Google Patents

Input/Output Control for a Digital Computing System.

Info

Publication number
GB1191560A
GB1191560A GB47311/68A GB4731168A GB1191560A GB 1191560 A GB1191560 A GB 1191560A GB 47311/68 A GB47311/68 A GB 47311/68A GB 4731168 A GB4731168 A GB 4731168A GB 1191560 A GB1191560 A GB 1191560A
Authority
GB
United Kingdom
Prior art keywords
word
character
buffer memory
memory
peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB47311/68A
Inventor
Erwin Arthur Hauck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Priority to GB47311/68A priority Critical patent/GB1191560A/en
Priority to DE19681801619 priority patent/DE1801619B2/en
Publication of GB1191560A publication Critical patent/GB1191560A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/02Input arrangements using manually operated switches, e.g. using keyboards or dials
    • G06F3/0227Cooperation and interconnection of the input arrangement with other functional units of a computer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Communication Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

1,191,560. Computer input/output. BURROUGHS CORP. 4 Oct., 1968, No. 47311/68. Heading G4A. In a computer system, an associative memory containing peripheral unit designators is used to address a buffer memory, data being transferred between the buffer memory and a peripheral unit. Input-Output.-An initiate signal from a central processor causes a peripheral control multiplexor to obtain an I/0 descriptor from main core memory and store a peripheral device (input, output, or bulk storage) designator from it in the first free row of an associative memory and store the whole descriptor (after repositioning of fields) in the corresponding row of a buffer memory in the multiplexor. An operation code from the descriptor is also sent to peripheral control units associated with respective peripheral devices, the one selected by a decoding of the device designator responding by sending an access request signal to the multiplexor on a respective line when it is ready. The highest priority access request is encoded to provide a (device designator) tag to interrogate the associative memory, and the row of this giving a match reads out the word in the corresponding row of the buffer memory to a word register, a character of data being transferred between this word and a register in the appropriate peripheral device control unit. The word from the buffer memory contains a main memory address, a word count, a character count and has 8 character positions for data. The characters in the character positions are shifted along while the word is in the word register so that a character from the peripheral device control unit can be inserted into the rightmost position or supplied to the peripheral device control unit from the leftmost position according to the direction of transfer. The character count is incremented after each character transfer and the word restored into the buffer memory (permitting an access request from a higherpriority peripheral to be serviced). When the character count indicates the 8 character positions are full (on input) or empty (on output), an 8-character data word is transferred between the word register and the main memory address specified by the buffer memory word, in the appropriate direction. This address is then incremented, the word count decremented, and the character count reset to zero. When the word count reaches zero (end of operation) the appropriate row of the associative memory is cleared. The initial values of the main memory address and word count in the buffer memory word came from the descriptor. Access requests (see above) from the peripherals have priority over initiate signals (see above) from the processor in use of the associative memory.
GB47311/68A 1968-10-04 1968-10-04 Input/Output Control for a Digital Computing System. Expired GB1191560A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB47311/68A GB1191560A (en) 1968-10-04 1968-10-04 Input/Output Control for a Digital Computing System.
DE19681801619 DE1801619B2 (en) 1968-10-04 1968-10-07 DATA TRANSFER CONTROL UNIT IN A DATA PROCESSING SYSTEM

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB47311/68A GB1191560A (en) 1968-10-04 1968-10-04 Input/Output Control for a Digital Computing System.
DE19681801619 DE1801619B2 (en) 1968-10-04 1968-10-07 DATA TRANSFER CONTROL UNIT IN A DATA PROCESSING SYSTEM

Publications (1)

Publication Number Publication Date
GB1191560A true GB1191560A (en) 1970-05-13

Family

ID=25756227

Family Applications (1)

Application Number Title Priority Date Filing Date
GB47311/68A Expired GB1191560A (en) 1968-10-04 1968-10-04 Input/Output Control for a Digital Computing System.

Country Status (2)

Country Link
DE (1) DE1801619B2 (en)
GB (1) GB1191560A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2108677A5 (en) * 1970-09-30 1972-05-19 Siemens Ag
WO1991002312A1 (en) * 1989-08-08 1991-02-21 Cray Research, Inc. Modular input/output system for supercomputers

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2150931C3 (en) * 1971-10-13 1981-11-26 SIEMENS AG AAAAA, 1000 Berlin und 8000 München Circuit arrangement for entering information into a data processing system
US4334287A (en) * 1979-04-12 1982-06-08 Sperry Rand Corporation Buffer memory arrangement

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2108677A5 (en) * 1970-09-30 1972-05-19 Siemens Ag
WO1991002312A1 (en) * 1989-08-08 1991-02-21 Cray Research, Inc. Modular input/output system for supercomputers
US5347637A (en) * 1989-08-08 1994-09-13 Cray Research, Inc. Modular input/output system for supercomputers

Also Published As

Publication number Publication date
DE1801619C3 (en) 1974-02-07
DE1801619B2 (en) 1973-07-05
DE1801619A1 (en) 1970-06-04

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee