GB1188436A - Improvements in and relating to Digital Computers - Google Patents
Improvements in and relating to Digital ComputersInfo
- Publication number
- GB1188436A GB1188436A GB4474068A GB4474068A GB1188436A GB 1188436 A GB1188436 A GB 1188436A GB 4474068 A GB4474068 A GB 4474068A GB 4474068 A GB4474068 A GB 4474068A GB 1188436 A GB1188436 A GB 1188436A
- Authority
- GB
- United Kingdom
- Prior art keywords
- descriptor
- mother
- field
- address
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002093 peripheral effect Effects 0.000 abstract 10
- 238000003491 array Methods 0.000 abstract 1
- 230000004048 modification Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
1,188,436. Addressing data stores; computers. BURROUGHS CORP. 20 Sept., 1968 [25 Sept., 1967], No. 44740/68. Headings G4A and G4C. Address manipulation circuitry for a digital computer comprises a computer memory, a peripheral memory, and a source of copy descriptors and mother descriptors referencing information stored in groups of memory cells forming arrays in the computer memory, each mother descriptor including fields designating respectively: (1) the base address of an array in the computer memory or the array address in the peripheral memory, (2) length of array, (3) nature of field (1), each copy descriptor including fields designating respectively: (1) the base address of an array or the location of the mother descriptor of the array in the source, (2) the index value of a cell in the array relative to the base address, (3) nature of field (1), there being means responsive to an instruction to access a cell of the computer memory to address this memory with the sum of fields (1) and (2) of an appropriate copy descriptor if field (3) of this descriptor designates field (1) as containing a base address. General.-The computer memory includes a last-in-first-out stack to hold the descriptors (see above) but the locations of the stack are also addressable randomly by a memory address register also used for addressing the rest of the computer memory. The peripheral (back-up) memory may be a disc file or magnetic tape. Besides the fields mentioned above, each descriptor includes a field (4) specifying the descriptor as mother or copy. During operation, fields (3) and (4) are consulted and updated as appropriate. In the course of generation of the descriptors, a mother descriptor is generated for information in an array the first time it is referenced and a copy descriptor on each subsequent reference, so all the copy descriptors related to a given mother descriptor lie above it in the stack. Accessing a cell of computer memory.-A computer-memory-access instruction causes the top descriptor in the stack to be obtained. If it is a copy descriptor with a base address in field (1), fields (1) and (2) are added and used to address the computer memory. If it is a copy descriptor with a mother descriptor address in field (1), this address is used to access this mother descriptor from the stack. If the mother descriptor has a peripheral address in field (1), the computer programme is interrupted and fields (1) and (2) of the mother descriptor are used to obtain the array from peripheral memory, this array being stored in an unused portion of computer memory and its new base address being substituted for the peripheral address in field (1) of the mother descriptor. Thus if the mother descriptor did not initially have a base address in field (1) it has now, and in either case the base address is transferred to field (1) of the copy descriptor and added to field (2) of the copy descriptor to address the computer memory. If, alternatively, the original descriptor is a mother descriptor it is treated like the mother descriptor referred to above up to the point where it contains a base address in field (1), when an index value is inserted in field (2) and the sum of these fields is used to address the computer memory. As a modification, field (2) of either type of descriptor could contain an index value or an array length, a further field of the descriptor indicating which and causing replacement of a length by an index value from the stack before addition. Updating descriptors (see above also).-When an array has to be returned from peripheral to computer memory as described above, but there is no room, an array has to be transferred to the peripheral memory to make room. The computer memory is addressed to obtain (from the stack) the mother descriptor relating to the array to be sent to peripheral memory and field (1) of each descriptor above this mother descriptor in the stack is compared with field (1) of the mother descriptor, being replaced with the address in memory of the mother descriptor if equal. Finally, the peripheral address of the array is inserted into field (1) of the mother descriptor. All the descriptors are returned to their locations in the stack after use. Reference is made to Specification 1,188,435.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US67030467A | 1967-09-25 | 1967-09-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1188436A true GB1188436A (en) | 1970-04-15 |
Family
ID=24689867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4474068A Expired GB1188436A (en) | 1967-09-25 | 1968-09-20 | Improvements in and relating to Digital Computers |
Country Status (5)
Country | Link |
---|---|
BE (1) | BE721403A (en) |
CA (1) | CA920277A (en) |
DE (1) | DE1774866C3 (en) |
FR (1) | FR1604610A (en) |
GB (1) | GB1188436A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985004031A1 (en) * | 1984-03-02 | 1985-09-12 | Goran Anders Hendrik Hemdal | Virtual address to real address conversion |
-
1968
- 1968-09-20 GB GB4474068A patent/GB1188436A/en not_active Expired
- 1968-09-24 CA CA030718A patent/CA920277A/en not_active Expired
- 1968-09-24 DE DE19681774866 patent/DE1774866C3/en not_active Expired
- 1968-09-25 BE BE721403D patent/BE721403A/xx not_active IP Right Cessation
- 1968-09-25 FR FR1604610D patent/FR1604610A/fr not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985004031A1 (en) * | 1984-03-02 | 1985-09-12 | Goran Anders Hendrik Hemdal | Virtual address to real address conversion |
AU569615B2 (en) * | 1984-03-02 | 1988-02-11 | Hemdal, G.A.H. | Improvements in or relating to computers |
US4922415A (en) * | 1984-03-02 | 1990-05-01 | Hemdal Goran A H | Data processing system for converting virtual to real addresses without requiring instruction from the central processing unit |
Also Published As
Publication number | Publication date |
---|---|
BE721403A (en) | 1969-03-03 |
DE1774866B2 (en) | 1978-08-03 |
DE1774866C3 (en) | 1979-04-05 |
CA920277A (en) | 1973-01-30 |
FR1604610A (en) | 1972-01-03 |
DE1774866A1 (en) | 1971-04-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |