GB1184721A - Improvements in or relating to Electronic Switching Apparatus - Google Patents

Abstract

1,184,721. Transistor switching circuits; circuits employing bi-stable magnetic elements. HONEYWELL Inc. 27 Feb., 1967 [23 March, 1966], No. 9271/67. Headings H3B and H3T. [Also in Division G4] A transistor switch feeding a reactive load has means responsive to the load voltage which increases the drive to the transistor control electrode during the switching-on transient. In the monolithic circuit of Fig. 3 the coincident application of positive signals to the emitters 49 or transistor 48 diverts the base current to the base of 55 rendering 55 and 27 conducting so that, if switch 47 is made current, current builds up in the magnetic storage matrix line 63. As the build up occurs the potential at 41 falls, eventually cutting off transistor 62 and thus reducing the base drive current force 27 provided through 55. Power dissipation and turn off time are thereby reduced. The voltage supplied to line 63 is limited by a diode 40 or if this fails by transistor 62. Resistor 66 discharges the matrix line capacitance during switch off and serves with an adjacent layer of opposite conductivity type to form a diode which absorbs back e.m.f. generated across the matrix line. Diodes 67 and 61 protect transistor 62 against excessive reverse voltage. Fig. 4 shows the circuit of switch 47 of Fig. 3. Concurrent application of positive signals to emitters 71 diverts the current flowing through transistor 73 to collector 46, switching on transistors 78, 80 and 25. Overdrive is initially applied to the base of transistor 25 through a diode 82 and transistor 80 but this diode becomes non-conductive as the voltage drop across 36 increases. Again, the voltage to which the drive line terminal builds up is limited by diode 40. Resistors 74 and 75 are arranged to track with temperature to stabilize the bias on transistor 73 and diode 83 discharges base capacitance between transistors 25 and 80. Two pairs of the above circuits may be formed on a single ship (Fig. 5, not shown), the output transistors 25, 27, 125, 127 forming the selection and drive unit 30 of Fig. 2 (see below). A single drive enhancing transistor 62 and a single constant current transistor 73 serve for a pair of circuits. An additional multi-emitter gate (102) feeds address and data signals to extra emitters of the input transistors 48, 70. Fig. 2 shows the basic arrangement of the matrix Y drive lines. Unit 30 is as described above, unit 35 is a separate ship and the isolating diodes 23, 26 are on a further ship. One constant current and limiter circuit 37 to 51 (of the type described above) serves several circuits that are not in use simultaneously. As described with reference to Fig. 6 (not shown) it uses two cores per bit and is word organized. There are three windings of each core, the inhibit winding being omitted and this function being added to the Y axis logic. The half current pulse system is used. The store may be of folded construction (Fig. 7, not shown) the X axis drive and selection ships being mounted on the top card and the Y chips along two opposite edges of the cards carrying the storage elements.