GB1172103A - Improvements relating to Data Processing Systems - Google Patents

Abstract

1,172,103. Data processing systems; data storage. PLESSEY CO. Ltd. 24 May, 1968 [30 May, 1967], No. 24830/67. Headings G4A and G4C. A data processing system comprises a main store holding the information for each programme in two discrete parts, viz. the data words and the instruction words respectively, each part being stored separately using sequentially numbered pages (multi-word storage sections), there being three registers holding codes respectively indicative of: (a) the first page (base page) holding date words of the operative programme (relocation register); (b) the page in which the data word currently being processed is stored (page register); (c) the address of the instruction word currently controlling the system (sequence control register). As described there are 256 pages, each of 256 words. Obtaining operand addresses.-If an " indirect address " tag in the current instruction word is O, an 8-bit address field of the instruction is concatenated (as the low order portion) with the contents of the 8-bit page register to form the operand (data word) address, except that if a " modifier " tag in the instruction is 1 the contents of a 16-bit modifier register are added. If the " indirect address " tag is 1, the same occurs except that the 8-bit relocation register is used instead of the page register and the resulting address is used to obtain an indirect address word from the store (base page). If a " common data " tag in this address word is 1, a 13-bit address portion of the word is used (with or without modification as before under control of a " modifier " tag in the word) to access data common to a plurality of programmes. Otherwise if an " indirect address " tag of the indirect address word is O, the address portion is used as the operand address (with or without "modification " as before) whereas if this tag is 1, the address portion and the contents of the relocation register are added to obtain (with or without " modification " as before) the address of another indirect address word, and so on. The page register is updated as appropriate. A guard register restricts addressing to the area allocated to the operative programme except in a " common data access. Obtaining the next instruction.-Normally the 16-bit sequence control register is merely incremented by one. However, a single length jump instruction contains a 7-bit address portion which is added to or subtracted from the sequence control register according to a sign bit in the instruction. A " modifier " tag in the instruction, if 1, causes the contents of the modifier register to be added in as well. A double length jump instruction (i.e. consisting of two consecutive words) has a 13-bit address portion in the second word which can be used and modified like the address portion of the single length jump instruction under control of tags and a sign bit, or can be added with the contents of the relocation register to form (with or without modification by the contents of the modifier register as before) the address of an indirect address word which either contains an address to be added to or subtracted from the contents of the sequence control register as before or the address of another indirect address word and so on (with or without modification in either case). Another double length jump instruction, used for returning from a subroutine, holds the absolute address of the instruction to be returned to in the 16 bits of the second word. This absolute address is simply overwritten into the sequence control register. There may be a list of such absolute return addresses in which case the contents of the sequence control register and modifierregister are added to obtain the address of the appropriate word in the list. Other features.-The main store may be a core store periodically loaded from a back-up magnetic tape or drum store. Two-address instruction words may be used, instead of oneaddress words as above.