GB1154467A - Computer Unit for Obtaining the Logarithms of Binary Numbers - Google Patents

Abstract

1,154,467. Determination of approximate logarithms. EUROPEAN ATOMIC ENERGY COMMUNITY (EURATOM). 22 Aug., 1966 [31 Aug., 1965], No. 37561/66. Heading G4A. A computer unit which determines the logarithm to a base of two of binary numbers N by using the approximation given whole number values of k and where o # x <1 by means of a shift register in which the value of x is formed by the repeated shift of N until the most significant digit is delivered by the register, the value k being obtained by counting of shift steps, is characterised in that the shift register is capable of cumulative adding and is connected to a correction system which adds various correction factors (constants and/or functions of x) to the value of x, dependent on the value of x and that for the purpose of establishing functions of x, a further shift register is provided. The preferred correction factors are as set out below: Correction = <SP>5</SP>/ 16 x when 0 # x < “ Correction = <SP>5</SP>/ 64 " “ # x < ¢ Correction = #x + <SP>3</SP>/ 128 " ¢ # x < ¥ Correction = “x " ¥ # x < 1 In the embodiment shown, the number N is fed under control of control unit 17 from an external source connected to terminal 11 into a sevenstage shift register 13, the shifting continuing until the most significant bit overflows into the first stage of a second seven-stage shift register 16. The bits remaining in register 13 then comprise the factor x. The factor k is determined using a counter 15 which is counted down step by step from the value 7, the counting effectively starting at the point at which the integral part of N is just loaded into the register 13. The particular correction to be applied is determined by outputs from the two most significant stages of register 13, which outputs are connected in the four possible normal and inverted combinations to AND-gates 18-21. Thus, when a timing pulse b is issued by control unit 17, one only of the gates 18-21 will be enabled and a corresponding one or ones of flipflops 22 set. These flip-flops are connected to further AND-gates, each of which is associated with a particular correction factor and each of which has a timing input from the control unit 17. Those AND-gates associated with functions of x have a third input connected to the most significant stage of a further shift register 14 which was fed with the same signals as register 13 (i.e. also contains x). The arrangement is such that, after the required function or functions of the most significant bit of x has or have been calculated and added into register 13, the register 13, 14 and 16 are stepped-on one position and the next bit of x dealt with. After the function of x corrections have been applied for all 7 bits in register 14, the amended value of x now located in register 16 has the constant corrections applied thereto.