GB1153420A - Improvements in Data Processing Systems - Google Patents
Improvements in Data Processing SystemsInfo
- Publication number
- GB1153420A GB1153420A GB2217768A GB2217768A GB1153420A GB 1153420 A GB1153420 A GB 1153420A GB 2217768 A GB2217768 A GB 2217768A GB 2217768 A GB2217768 A GB 2217768A GB 1153420 A GB1153420 A GB 1153420A
- Authority
- GB
- United Kingdom
- Prior art keywords
- interrupt
- programme
- list
- address
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
Abstract
1,153,420. Computer interrupt. INTERNATIONAL BUSINESS MACHINES CORP. 10 May, 1968, No. 22177/68. Heading G4A. In a data processing system, an interrupt condition causes the status of the current programme to be stored in a first area, a second area to be allocated to a new programme, and the address of the first area to be entered into the second area. In a two-processor microprogramme-controlled system, the highest priority interrupt request not masked by a status register selects a double-word from a (stored) interrupt list according to the class of interrupt. The doubleword includes a bit-pair and an address. If the bit-pair is 01, 10 or 11, the address is that of an interrupt class list. If the bit-pair is 01, the interrupt code (which gives details of the interrupt) is shifted and used to select another double-word from the interrupt class list. If the bit-pair is 10, the interrupt code is decremented by a so-called "mask" in the interrupt class list and one of two double-words selected from this list according as the result is negative or not. If the bit-pair is 11, the interrupt code is ANDed with the "mask" and one of the two doublewords selected according as the result is zero or not. If the bit-pair is 00, the address is that of a status load block. In this way a sequence of one or more double-words is selected until one is reached with the bit-pair 00 to obtain the address of a status load block. In the above, if the interrupt code is decremented, it is the decremented interrupt code which is used, if necessary, in connection with the next double-word, but if it is ANDed, it is the code before ANDing which is used. The status load block is used to initialize the system to execute the programme for dealing with the interrupt, after storing the current status data (relating to the interrupted programme) in a current programme status block (storage area), to enable subsequent resumption of the interrupted programme. A programme status block is obtained for the new programme, the address of this block being obtained from the head of the interrupt list which specifies the address of the first block of a free list of such blocks, each block in the list containing the address of the next so that they are chained together. The "first block" address in the interrupt list is then updated. While the interrupt list is being used by one processor, a lock byte and the identity of the processor are stored in it (the list) to prevent the other processor using it and to enable this processor to find out why use is prevented. The programme status block (which is loaded With status data for its programme when that programme is interrupted) holds interrupt masking bits, storage protection key (for comparison with a key associated with each block of storage to prevent access unless they are equal or one is zero), instruction length indicator, indication of conditions which will cause branch, next instruction address, indications of which local storage registers have had their contents saved (determined by the doubleword with bit-pair 00 referred to above), addresses of locations where various registers can be dumped in the event of an interrupt, the address of the programme status block of the previously running programme, class of interrupt, identity of processor to which the current interruption is related, interrupt code, and extended interrupt code giving more information on the interrupt. Provision is made for dealing with exhaustion of the free list. Conventional types of interrupt are described. The interrupt list, interrupt class lists and status load blocks are settable under control of a supervisor programme. Besides the two processors, the system includes two memories with a unified addressing scheme and the effective configuration of the system is controlled by configuration control data stored in the various units.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2217768A GB1153420A (en) | 1968-05-10 | 1968-05-10 | Improvements in Data Processing Systems |
DE19691923291 DE1923291A1 (en) | 1968-05-10 | 1969-05-07 | Device for controlling program interruptions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2217768A GB1153420A (en) | 1968-05-10 | 1968-05-10 | Improvements in Data Processing Systems |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1153420A true GB1153420A (en) | 1969-05-29 |
Family
ID=10175202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2217768A Expired GB1153420A (en) | 1968-05-10 | 1968-05-10 | Improvements in Data Processing Systems |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE1923291A1 (en) |
GB (1) | GB1153420A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0311187A1 (en) * | 1987-10-08 | 1989-04-12 | Koninklijke Philips Electronics N.V. | Interface device for interfacing a network station to a physical network medium |
WO2010004243A2 (en) * | 2008-07-10 | 2010-01-14 | Cambridge Consultants Limited | Interrupt processing |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL7409218A (en) * | 1973-10-19 | 1975-04-22 | Texas Instruments Inc | UNIVERSAL DIGITAL COMPUTER. |
-
1968
- 1968-05-10 GB GB2217768A patent/GB1153420A/en not_active Expired
-
1969
- 1969-05-07 DE DE19691923291 patent/DE1923291A1/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0311187A1 (en) * | 1987-10-08 | 1989-04-12 | Koninklijke Philips Electronics N.V. | Interface device for interfacing a network station to a physical network medium |
WO2010004243A2 (en) * | 2008-07-10 | 2010-01-14 | Cambridge Consultants Limited | Interrupt processing |
WO2010004243A3 (en) * | 2008-07-10 | 2010-03-04 | Cambridge Consultants Limited | Interrupt processing |
Also Published As
Publication number | Publication date |
---|---|
DE1923291A1 (en) | 1969-12-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |