GB1140103A - A bistable flip-flop - Google Patents
A bistable flip-flopInfo
- Publication number
- GB1140103A GB1140103A GB2425566A GB2425566A GB1140103A GB 1140103 A GB1140103 A GB 1140103A GB 2425566 A GB2425566 A GB 2425566A GB 2425566 A GB2425566 A GB 2425566A GB 1140103 A GB1140103 A GB 1140103A
- Authority
- GB
- United Kingdom
- Prior art keywords
- flip
- flop
- state
- gates
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/084—Diode-transistor logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0372—Bistable circuits of the master-slave type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
1,140,103. Bistable flip-flop for use in digital computers. SCIENTIFIC DATA SYSTEMS Inc. 31 May, 1966 [1 June, 1965], No. 24255/66. Heading G4C. [Also in Division H3] A bistable flip-flop having set and reset states and comprising a master portion having two output circuits connected to a slave portion, the two output circuits consisting of two coincidence circuits each being responsive to a clock signal alternating between first and second states and each being responsive to input signals that when either flip-flop state exists the corresponding coincidence circuit provides a clock dependent output and the other coincidence provides a clock independent output, and when one flipflop state exists and an input signal for switching the flip-flop to its other state is recieved during a first clock state the coincidence circuit corresponding to the existing flip-flop state is rendered clock-independent, thereby preventing the output thereof from changing when the clock signal changes state and thereby establishing the other flip-flop state when the clock signal changes state, the slave portion comprising two gates connected to receive the outputs of the coincidence circuits respectively and each cross-coupled. Absence of erase signal (E = 0).-In the unit shown in Fig. 2 GSR, GE, GR, GS and GQ are AND gates N2, N3, N4, N5, NR and NS are NOR gates I1, I2, I3 and N1. are inverters and A stands for amplifier. Assuming E = 0 causes AND gates GE and GQ to be enabled. The master flip-flop is set or reset when the clock pulse changes from a true state to a false state. If this has occured, the Boolean equation for GS is while the clock pulse C is false i.e. gates GR, GS are enabled. Thus regardless of the value of S or R, GS remains unaltered and hence so does GR. During the following true clock pulse states AND gates GR, GS are both inhibited, however, the slave flip-flop maintains the state previously maintained by the master flip-flop. At the next change of state of the clock pulses from true to false the equations apply i.e. if a set signal S occurs regardless of the presence of a reset R signal GS is enabled and GR inhibited. If only a reset signal is present GR is enabled regardless of the previous value of the flip-flop. If neither set nor reset pulses occur then the master flip-flop returns to its previous state i.e. if #Q=l then GR is enabled, if #Q = 0 then GS is enabled. Presence of erase signal (E = 1) .-If an erase signal is applied AND gates GE and GO are inhibited. GR will be enabled on the change over from a true clock pulse to a false clock pulse and GO will be inhibited to render Q = 0. The feed-back paths will maintain appropriate signals at the other gates GS, NR. The gates are provided by transistor circuits (Fig. 3, not shown) the amplifier being a common base amplifier, the inverter being a common emitter amplifier, the NOR gate being formed from two inverters having their collectors coupled and their emitters coupled to form parallel collector-emitter paths, and the AND gates being formed by connecting together the outputs from the previous gates. A circuit is described (Fig. 4, not shown), for converting voltage levels in different portions of a data processing machine using the flip-flops to feed various logic circuits and being controlled by counter and further flip-flops to perform processing operations.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US46040865A | 1965-06-01 | 1965-06-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1140103A true GB1140103A (en) | 1969-01-15 |
Family
ID=23828589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2425566A Expired GB1140103A (en) | 1965-06-01 | 1966-05-31 | A bistable flip-flop |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS5246064B1 (en) |
DE (1) | DE1524217B2 (en) |
GB (1) | GB1140103A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109462394A (en) * | 2017-09-06 | 2019-03-12 | 三星电子株式会社 | Sequence circuit |
-
1966
- 1966-05-28 DE DE19661524217 patent/DE1524217B2/en not_active Ceased
- 1966-05-31 GB GB2425566A patent/GB1140103A/en not_active Expired
-
1969
- 1969-11-28 JP JP44095140A patent/JPS5246064B1/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109462394A (en) * | 2017-09-06 | 2019-03-12 | 三星电子株式会社 | Sequence circuit |
CN109462394B (en) * | 2017-09-06 | 2023-10-20 | 三星电子株式会社 | sequential circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5246064B1 (en) | 1977-11-21 |
DE1524217B2 (en) | 1971-04-22 |
DE1524217A1 (en) | 1970-07-30 |
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