GB1138549A - A memory device and method for producing a memory device - Google Patents

Abstract

1,138,549. Read only stores. LITTON INDUSTRIES Inc. 14 Nov., 1966 [26 Nov., 1965], No. 51013/66. Heading G4A. A word organized permanent magnetic linear select memory comprises plural magnetic memory cores in plane 10, and word select cores in plane 12; embedded in substrate 88 (Fig. 1). Cores 14, 16, 18, 20 assigned to bits 1, 2, 3, 4 of word 1 are energized by loop 64 from word select core 22, while cores 24, 26, 28, 30; 34, 36, 38, 40, 44, 46, 48, 50 assigned respectively to bits 1, 2, 3, 4 of words 2, 3, 4 are energized by loops 66, 68, 70 from word select cores 32, 42, 52. Bias source 54 energizes word select cores 52, 32, 22, 42 with current IB while bias source 56 energizes word select cores 22, 32 with current I X1 , bias source 58 energizes cores 42, 52 with current I X2 , bias source 60 energizes cores 42, 22 with current I y1 , and bias source 62 energizes cores 32, 52 with current I y2 ; all sensed to oppose the magnetic effect of current I B . Bit sensing lines 90, 92, 94, 96 threading respective columns of 1st, 2nd, 3rd and 4th bit cores in plane 10 are connected to terminal pairs 72, 74; 76, 78; 80, 82; 84, 86; and initially all cores are set to a stable magnetic state, after which selected cores are broken, e.g. through an apertured template, and an intact core stores information representing " 1 " (or " 0 ") while a broken core stores information representing " 0 " (or " 1 "). E.g. in Fig. 1, the stored words Nos. 1, 2, 3, 4 are 1011, 1001, 0101, 0011 in direct (or 0100, 0110, 1010, 1100 in complementary) arithmetic. Each word select core has rectangular BH curve (Fig. 3) with bias field H at 100. Squarewave current pulses I y , I x2 (Fig. 4) generate field increments H y1 , H y2 opposing the bias to increase H from 100 to 112 for one and to 114 for both increments, whereby B increases from 110 to 116 and a current pulse 118 is applied over loop 68 to memory cores 34, 36, 38, 40 which change state so that cores 36, 40 generate pulses 120, 122 on bit sensing lines to terminals 76, 78; 84, 86, while cores 34, 38 generate only noise 124, 126 on the lines to terminals 72, 74; 80, 82. On removal of currents B reverts and a reverse current pulse 128 over loop 68 resets cores 36, 40 to generate reverse pulses 120, 122 on the appropriate bit sensing lines. Additional word select cores 22, 32, 52 and memory core rows 14, 16, 18, 20; 24, 26, 28, 30; 44, 46, 48, 50 corresponding to different words of the memory are similarly operated to pulse corresponding bit sensing lines, which are assigned to predetermined bit numbers looping all cores of the words corresponding thereto.