GB1136717A - Magnetic core memory equipped with a safety circuit - Google Patents

Abstract

1,136,717. Data protection arrangement. INTERNATIONAL STANDARD ELECTRIC CORP. 7 April, 1966 [15 April, 1965], No. 15568/66. Heading G4C. [Also in Division H3] In a magnetic core memory with destructive read-out and restoring means for rewriting the contents of an address immediately after read-out and having a safety device for blocking operation of the memory when supply voltages vary beyond predetermined upper and lower limits, integrity of stored data is ensured in that said blocking can only occur in the time interval between a re-write time slot and the next succeeding read time slot. In the system described (Fig. 1) safety circuits SC interposed between a memory MR and its sources of stabilized voltages 11A, 11B and 11C supplied from non-regulated source U comprise in each supply line 2A, 2B and 2C a detection circuit 12A, 12B or 12C. Each circuit 12 consists of a double threshold amplitude discriminator 15 and a delay circuit 16. On detection by one of the discriminators 15 of a voltage outside said two threshold values, an alarm signal S is passed by way of a line 3 and an OR- gate 17 to one input of an AND-gate 18. The other input of this AND-gate receives clock pulses P which occur in the intervals between the time slots for rewriting at one address and reading at another address. The output 5 of AND-gate 18 sets bi-stable device 14 which then issues a blocking signal 7 to memory MR. The delay circuits 16 are included to allow for the fact that there may be a delay of almost one complete read-write cycle between the generation of the alarm signal S and the application of blocking signal 7 to the memory MR. After the alarm condition has ceased, AND gate 19 becomes enabled (20 being an inverter and 21 a delay device) whereby at the next pulse P the output 6 resets the bi-stable device 14 for unblocking memory MR. Details of a discriminator 12 (employing two Zener diodes, two NPN transistors and two ordinary diodes) and a delay circuit 16 (comprising a diode and a capacitor) are given with reference to Fig. 4 (not shown). Fig. 5 (not shown) illustrates a transistorized bi-stable circuit 14 with a transistorized circuit (50) coupled thereto for forcing the circuit 14 into its reset state for blocking of memory MR when starting the memory up initially.